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iip.htm
Enumerations
IipList
Grouphandlers
IipGroupAES
IipGroupBLEND
IipGroupCLMUL
IipGroupSSE
IipGroupSSE1
IipGroupSSE4
IipGroupSSE4_1
Instruction handlers
ADDPD ADDPS ADDSD ADDSS ADDSUBPD ADDSUBPS AESDEC AESDECLAST AESENC AESENCLAST AESIMC AESKEYGENASSIST ANDNPD ANDNPS ANDPD ANDPS BLENDPD BLENDPS BLENDVPD BLENDVPS CMPEQPD CMPEQPS CMPEQSD CMPEQSS CMPLEPD CMPLEPS CMPLESD CMPLESS CMPLTPD CMPLTPS CMPLTSD CMPLTSS CMPNEQPD CMPNEQPS CMPNEQSD CMPNEQSS CMPNLEPD CMPNLEPS CMPNLESD CMPNLESS CMPNLTPD CMPNLTPS CMPNLTSD CMPNLTSS CMPORDPD CMPORDPS CMPORDSD CMPORDSS CMPPD CMPPS CMPSS CMPUNORDPD CMPUNORDPS CMPUNORDSD CMPUNORDSS COMISD COMISS CRC32 CRC32B CRC32D CRC32Q CRC32W CVTDQ2PD CVTDQ2PS CVTPD2DQ CVTPD2PS CVTPS2DQ CVTPS2PD CVTSD2SI CVTSD2SS CVTSI2SD CVTSI2SS CVTSS2SD CVTSS2SI CVTTPD2DQ CVTTPS2DQ CVTTSD2SI CVTTSS2SI DIVPD DIVPS DIVSD DIVSS DPPD DPPS EXTRACTPS EXTRQ HADDPD HADDPS HSUBPD HSUBPS INSERTPS INSERTQ LDDQU LDMXCSR MASKMOVDQU MAXPD MAXPS MAXSD MAXSS MINPD MINPS MINSD MINSS MOVAPD MOVAPS MOVDDUP MOVDQA MOVDQU MOVHLPS MOVHPD MOVHPS MOVLHPS MOVLPD MOVLPS MOVMSKPD MOVMSKPS MOVNTDQ MOVNTDQA MOVNTI MOVNTPD MOVNTPS MOVNTSD MOVNTSS MOVSHDUP MOVSLDUP MOVSS MOVUPD MOVUPS MPSADBW MULPD MULPS MULSD MULSS ORPD ORPS PACKUSDW PBLENDVB PBLENDW PCLMULHQHQDQ PCLMULHQLQDQ PCLMULLQHQDQ PCLMULLQLQDQ PCLMULQDQ PCMPEQQ PCMPESTRI PCMPESTRM PCMPGTQ PCMPISTRI PCMPISTRM PEXTRB PEXTRD PEXTRQ PHMINPOSUW PINSRB PINSRD PINSRQ PMAXSB PMAXSD PMAXUD PMAXUW PMINSB PMINSD PMINUD PMINUW PMOVSXBD PMOVSXBQ PMOVSXBW PMOVSXDQ PMOVSXWD PMOVSXWQ PMOVZXBD PMOVZXBQ PMOVZXBW PMOVZXDQ PMOVZXWD PMOVZXWQ PMULDQ PMULLD PSHUFD PSHUFHW PSHUFLW PSLLDQ PSRLDQ PTEST PUNPCKHQDQ PUNPCKLQDQ RCPPS RCPSS ROUNDPD ROUNDPS ROUNDSD ROUNDSS RSQRTPS RSQRTSS SHUFPD SHUFPS SQRTPD SQRTPS SQRTSD SQRTSS STMXCSR SUBPD SUBPS SUBSD SUBSS UCOMISD UCOMISS UNPCKHPD UNPCKHPS UNPCKLPD UNPCKLPS XORPD XORPS

↑ IipHandlers: assemble SSE machine instructions with packed and scalar operands.
See also: IiHandlers, [IntelVol2].

iip PROGRAM FORMAT=COFF,MODEL=FLAT,WIDTH=32
 INCLUDEHEAD "euroasm.htm" ; Interface (structures, symbols and macros) of other modules.

iip HEAD ; Start ofmodule interface.

↑ %IipList: enumerates machine instructions of this family which €ASM can assemble.
Each instruction declared in %IipList requires the corresponding handler in this file.
See also: DictLookupIi

%IipList %SET \
AESIMC, \
AESENC, \
AESENCLAST, \
AESDEC, \
AESDECLAST, \
AESKEYGENASSIST, \
CRC32, \
CRC32B, \
CRC32W, \
CRC32D, \
CRC32Q, \
MOVNTPS, \
MOVNTPD, \
MOVNTI, \
MOVNTDQ, \
MOVNTDQA, \
EXTRACTPS, \
PEXTRB, \
PEXTRD, \
PEXTRQ, \
LDMXCSR, \
STMXCSR, \
MOVMSKPD, \
MOVMSKPS, \
PSRLDQ, \
PSLLDQ, \
CVTTSD2SI, \
CVTSD2SI, \
CVTSS2SI, \
CVTTSS2SI, \
CVTSI2SS, \
CVTSI2SD, \
PINSRB, \
PINSRD, \
PINSRQ, \
MOVUPS, \
MOVAPS, \
MOVLPS, \
MOVHPS, \
MOVHLPS, \
MOVLHPS, \
UNPCKLPS, \
UNPCKHPS, \
UCOMISS, \
COMISS, \
SQRTPS, \
RSQRTPS, \
RCPPS, \
ANDNPS, \
ANDPS, \
ORPS, \
XORPS, \
ADDPS, \
MULPS, \
CVTPS2PD, \
CVTDQ2PS, \
SUBPS, \
MINPS, \
DIVPS, \
MAXPS, \
MOVHPD, \
MOVLPD, \
MOVAPD, \
MOVSS, \
MOVUPD, \
PTEST, \
PMOVSXBW, \
PMOVSXBD, \
PMOVSXBQ, \
PMOVSXWD, \
PMOVSXWQ, \
PMOVSXDQ, \
PMULDQ, \
PCMPEQQ, \
PACKUSDW, \
PMOVZXBW, \
PMOVZXBD, \
PMOVZXBQ, \
PMOVZXWD, \
PMOVZXWQ, \
PMOVZXDQ, \
PCMPGTQ, \
PMINSB, \
PMINSD, \
PMINUW, \
PMINUD, \
PMAXSB, \
PMAXSD, \
PMAXUW, \
PMAXUD, \
PMULLD, \
PHMINPOSUW, \
UNPCKLPD, \
UNPCKHPD, \
UCOMISD, \
COMISD, \
SQRTPD, \
ANDPD, \
ANDNPD, \
ORPD, \
XORPD, \
ADDPD, \
MULPD, \
CVTPD2PS, \
CVTPS2DQ, \
SUBPD, \
MINPD, \
DIVPD, \
MAXPD, \
PUNPCKLQDQ, \
PUNPCKHQDQ, \
HADDPD, \
HSUBPD, \
ADDSUBPD, \
CVTTPD2DQ, \
MOVDDUP, \
SQRTSD, \
ADDSD, \
MULSD, \
CVTSD2SS, \
SUBSD, \
MINSD, \
DIVSD, \
MAXSD, \
HADDPS, \
HSUBPS, \
ADDSUBPS, \
CVTPD2DQ, \
MOVSLDUP, \
MOVSHDUP, \
SQRTSS, \
RSQRTSS, \
RCPSS, \
ADDSS, \
MULSS, \
CVTSS2SD, \
CVTTPS2DQ, \
SUBSS, \
MINSS, \
DIVSS, \
MAXSS, \
CVTDQ2PD, \
ROUNDPS, \
ROUNDPD, \
ROUNDSS, \
ROUNDSD, \
BLENDPS, \
BLENDPD, \
PBLENDW, \
INSERTPS, \
DPPS, \
MPSADBW, \
PCMPESTRM, \
PCMPESTRI, \
PCMPISTRM, \
PCMPISTRI, \
DPPD, \
SHUFPS, \
PSHUFD, \
SHUFPD, \
PSHUFLW, \
PSHUFHW, \
MOVDQA, \
MOVDQU, \
MASKMOVDQU, \
LDDQU, \
PCLMULQDQ, \
PCLMULLQLQDQ, \
PCLMULHQLQDQ, \
PCLMULLQHQDQ, \
PCLMULHQHQDQ, \
PBLENDVB, \
BLENDVPS, \
BLENDVPD, \
CMPEQSS, \
CMPLTSS, \
CMPLESS, \
CMPUNORDSS, \
CMPNEQSS, \
CMPNLTSS, \
CMPNLESS, \
CMPORDSS, \
CMPEQSD, \
CMPLTSD, \
CMPLESD, \
CMPUNORDSD, \
CMPNEQSD, \
CMPNLTSD, \
CMPNLESD, \
CMPORDSD, \
CMPEQPS, \
CMPLTPS, \
CMPLEPS, \
CMPUNORDPS, \
CMPNEQPS, \
CMPNLTPS, \
CMPNLEPS, \
CMPORDPS, \
CMPEQPD, \
CMPLTPD, \
CMPLEPD, \
CMPUNORDPD, \
CMPNEQPD, \
CMPNLTPD, \
CMPNLEPD, \
CMPORDPD, \
CMPPS, \
CMPSS, \
CMPPD, \
MOVNTSS, \
MOVNTSD, \
EXTRQ, \
INSERTQ, \

;

  ENDHEAD iip  ; End of module interface.

↑ IipGroupAES: IipGroupAES is a common handler for AES instructions in format xmm,xmm/mem with prefix 0x66 and three-byte opcode 0x0F,0x38,CL.
Input: CL is the tertiary opcode.
EDX has operand types as set by IiAssemble.
EDI is pointer to II structure with parsed operands.
Tested by: t4100

IipGroupAES:: PROC
     IiRequire 686,AES
     IiEncoding DATA=OWORD
     IiEmitPrefix OTOGGLE
     IiEmitOpcode 0x0F,0x38,ECX
     IiOpEn RM
     IiModRM /r
     IiDispatchFormat xmm.xmm, xmm.mem
.xmm.xmm:
.xmm.mem:
     RET
 ENDP IipGroupAES::

↑ AESIMC: Perform the AES InvMixColumn Transformation
Description: AESIMC
Tested by: t4100

IipAESIMC:: PROC
    MOV CL,0xDB
    JMP IipGroupAES:
 ENDP IipAESIMC::

↑ AESENC: Perform One Round of an AES Encryption Flow
Description: AESENC
Tested by: t4100

IipAESENC:: PROC
    MOV CL,0xDC
    JMP IipGroupAES:
 ENDP IipAESENC::

↑ AESENCLAST: Perform Last Round of an AES Encryption Flow
Description: AESENCLAST
Tested by: t4100

IipAESENCLAST:: PROC
    MOV CL,0xDD
    JMP IipGroupAES:
 ENDP IipAESENCLAST::

↑ AESDEC: Perform One Round of an AES Decryption Flow
Description: AESDEC
Tested by: t4100

IipAESDEC:: PROC
    MOV CL,0xDE
    JMP IipGroupAES:
 ENDP IipAESDEC::

↑ AESDECLAST: Perform Last Round of an AES Decryption Flow
Description: AESDECLAST
Tested by: t4100

IipAESDECLAST:: PROC
    MOV CL,0xDF
    JMP IipGroupAES:
 ENDP IipAESDECLAST::

↑ AESKEYGENASSIST: AES Round Key Generation Assist
Description: AESKEYGENASSIST

IipAESKEYGENASSIST:: PROC
     IiRequire 686,AES
     IiEmitPrefix OTOGGLE
     IiEmitOpcode 0x0F,0x3A,0xDF
     IiOpEn RM
     IiModRM /r
     IiEmitImm Operand3, BYTE
     IiDispatchFormat xmm.xmm.imm, xmm.mem.imm
.xmm.xmm.imm:
.xmm.mem.imm:
     RET
 ENDP IipAESKEYGENASSIST::

↑ CRC32: Accumulate CRC32 Value
Description: CRC32
Category: sse42
Operands: Gdqp,Eb | Gdqp,Evqp
Opcode: 0xF20F38F0 /r | 0xF20F38F1 /r
CPU: C2++
Documented: D⁴³
Tested by: t3725 t3865

IipCRC32:: PROC
    IiRequire 686,SSE4.2
    IiDataSize Operand2
    IiEmitPrefix REPNE
    IiEmitOpcode 0x0F,0x38
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat r32.r8, r32.m8, r32.r16, r32.m16, r32.r32, r32.m32, r64.r8, r64.m8, r64.r64,r64.m64
.r64.r8:
.r64.m8:
    IiEmitPrefix REX.W
.r32.r8:
.r32.m8:
     IiEmitOpcode 0xF0
     RET
.r64.r64:
.r64.m64:
    IiEmitPrefix REX.W
.r32.r32:
.r32.m32:
.r32.r16:
.r32.m16:
    IiEmitOpcode 0xF1
    RET
 ENDP IipCRC32::

↑ CRC32B: Accumulate CRC32 Value from Byte
Category: sse42
Operands: Gdqp,Eb | Gdqp,Evqp
Opcode: 0xF20F38F0 /r | 0xF20F38F1 /r
CPU: C2++
Documented: D⁴³
Tested by: t3725 t3865

IipCRC32B:: PROC
    IiSuffixed CRC32,B,Category=p
 ENDP IipCRC32B::

↑ CRC32W: Accumulate CRC32 Value from Word
Category: sse42
Operands: Gdqp,Eb | Gdqp,Evqp
Opcode: 0xF20F38F0 /r | 0xF20F38F1 /r
CPU: C2++
Documented: D⁴³
Tested by: t3725 t3865

IipCRC32W:: PROC
    IiSuffixed CRC32,W,Category=p
 ENDP IipCRC32W::

↑ CRC32D: Accumulate CRC32 Value from Dword
Category: sse42
Operands: Gdqp,Eb | Gdqp,Evqp
Opcode: 0xF20F38F0 /r | 0xF20F38F1 /r
CPU: C2++
Documented: D⁴³
Tested by: t3725 t3865

IipCRC32D:: PROC
    IiSuffixed CRC32,D,Category=p
 ENDP IipCRC32D::

↑ CRC32Q: Accumulate CRC32 Value from Qword
Category: sse42
Operands: Gdqp,Eb | Gdqp,Evqp
Opcode: 0xF20F38F0 /r | 0xF20F38F1 /r
CPU: C2++
Documented: D⁴³
Tested by: t3725 t3865

IipCRC32Q:: PROC
    IiSuffixed CRC32,Q,Category=p
 ENDP IipCRC32Q::

↑ MOVNTPS: Store Packed Single-FP Values Using Non-Temporal Hint
Description: MOVNTPS
Category: sse1,cachect
Operands: Mps,Vps
Opcode: 0x0F2B /r
CPU: P3+
Tested by: t3690

IipMOVNTPS:: PROC
    IiRequire 686,SSE
    IiEmitOpcode 0x0F,0x2B
    IiOpEn MR
    IiModRM /r
    IiDispatchFormat mem.xmm
.mem.xmm:
    RET
 ENDP IipMOVNTPS::

↑ MOVNTPD: Store Packed Double-FP Values Using Non-Temporal Hint
Description: MOVNTPD
Category: sse2,cachect
Operands: Mpd,Vpd
Opcode: 0x660F2B /r
CPU: P4+
Tested by: t3690

IipMOVNTPD:: PROC
    IiEmitPrefix OTOGGLE
    IiRequire SSE2
    JMP IipMOVNTPS
 ENDP IipMOVNTPD::

↑ MOVNTI: Store Doubleword Using Non-Temporal Hint
Description: MOVNTI
Category: sse2,cachect
Operands: Mdqp,Gdqp
Opcode: 0x0FC3 /r
CPU: P4+
Tested by: t3690

IipMOVNTI:: PROC
    IiRequire 686,SSE2
    IiEmitOpcode 0x0F,0xC3
    IiOpEn MR
    IiModRM /r
    IiDispatchFormat mem.r32, mem.r64
.mem.r64:
    IiEmitPrefix REX.W
.mem.r32:
    RET
 ENDP IipMOVNTI::

↑ MOVNTDQ: Store Double Quadword Using Non-Temporal Hint
Description: MOVNTDQ
Category: sse2,cachect
Operands: Mdq,Vdq
Opcode: 0x660FE7 /r
CPU: P4+
Tested by: t3690

IipMOVNTDQ:: PROC
    IiRequire 686,SSE2
    IiEmitPrefix OTOGGLE
    IiEmitOpcode 0x0F,0xE7
    IiOpEn MR
    IiModRM /r
    IiDispatchFormat mem.xmm
.mem.xmm:
    RET
 ENDP IipMOVNTDQ::

↑ MOVNTDQA: Load Double Quadword Non-Temporal Aligned Hint
Description: MOVNTDQA
Category: sse41,cachect
Operands: Vdq,Mdq
Opcode: 0x660F382A /r
CPU: C2++
Documented: D⁴³
Tested by: t3690

IipMOVNTDQA:: PROC
    IiRequire 686,SSE4
    IiEmitPrefix OTOGGLE
    IiEmitOpcode 0x0F,0x38,0x2A
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat xmm.mem
.xmm.mem:
    RET
 ENDP IipMOVNTDQA::

↑ EXTRACTPS: Extract Packed Single-FP Value
Description: EXTRACTPS
Category: sse41,simdfp,datamov
Operands: Ed,Vdq,Ib
Opcode: 0x660F3A17 /r
CPU: C2++
Documented: D⁴³
Tested by: t3695

IipEXTRACTPS:: PROC
    IiRequire 686,SSE4
    IiEmitPrefix OTOGGLE
    IiEmitOpcode 0x0F,0x3A,0x17
    IiOpEn MR
    IiModRM /r
    IiEmitImm Operand3, BYTE
    IiDispatchFormat r32.xmm.imm, r64.xmm.imm, mem.xmm.imm
.r64.xmm.imm:
    IiEncoding DATA=QWORD    
    IiEmitPrefix REX.W
.r32.xmm.imm:
.mem.xmm.imm:
    IiEncoding DATA=DWORD
    RET
 ENDP IipEXTRACTPS::

↑ PEXTRB: Extract Byte
Description: PEXTRB
Category: sse41,simdint,datamov
Operands: Mb,Vdq,Ib | Rdqp,Vdq,Ib
Opcode: 0x660F3A14 /r | 0x660F3A14 /r
CPU: C2++
Documented: D⁴³
Tested by: t3695

IipPEXTRB:: PROC
    IiRequire 686,SSE4
    IiEncoding DATA=BYTE
    IiEmitPrefix OTOGGLE
    IiEmitOpcode 0x0F,0x3A,0x14
    IiOpEn MR
    IiModRM /r
    IiEmitImm Operand3, BYTE
    IiDispatchFormat r64.xmm.imm, r32.xmm.imm, mem.xmm.imm
.r64.xmm.imm:
    IiEmitPrefix REX.W
    IiEncoding DATA=QWORD
    RET
.r32.xmm.imm:
    IiEncoding DATA=DWORD
.mem.xmm.imm:
    RET
 ENDP IipPEXTRB::

↑ PEXTRD: Extract Dword
Description: PEXTRD
Category: sse41,simdint,datamov
Operands: Ed,Vdq,Ib
Opcode: 0x660F3A16 /r
CPU: C2++
Documented: D⁴³
Tested by: t3695

IipPEXTRD:: PROC
    IiRequire 686,SSE4
    IiEncoding DATA=DWORD
    IiEmitPrefix OTOGGLE
    IiEmitOpcode 0x0F,0x3A,0x16
    IiOpEn MR
    IiModRM /r
    IiEmitImm Operand3, BYTE
    IiDispatchFormat r32.xmm.imm, mem.xmm.imm
.r32.xmm.imm:
.mem.xmm.imm:
    RET
 ENDP IipPEXTRD::

↑ PEXTRQ: Extract Qword
Description: PEXTRQ
Category: sse41,simdint,datamov
Operands: Eqp,Vdq,Ib
Opcode: 0x660F3A16 /r
CPU: C2++
Documented: D⁴³
Tested by: t3695

IipPEXTRQ:: PROC
    IiRequire 686,SSE4
    IiEncoding DATA=QWORD
    IiEmitPrefix OTOGGLE, REX.W
    IiEmitOpcode 0x0F,0x3A,0x16
    IiOpEn MR
    IiModRM /r
    IiEmitImm Operand3, BYTE
    IiDispatchFormat r64.xmm.imm, mem.xmm.imm
.r64.xmm.imm:
.mem.xmm.imm:
    RET
 ENDP IipPEXTRQ::

↑ LDMXCSR: Load MXCSR Register
Description: LDMXCSR
Category: sse1,mxcsrsm
Operands: Md
Opcode: 0x0FAE /2
CPU: P3+
Tested by: t3700

IipLDMXCSR:: PROC
    IiModRM /2
.rm:IiRequire SSE
    IiEncoding DATA=DWORD
    IiEmitOpcode 0x0F,0xAE
    IiOpEn M
    IiDispatchFormat mem
.mem:RET
 ENDP IipLDMXCSR::

↑ STMXCSR: Store MXCSR Register State
Description: STMXCSR
Category: sse1,mxcsrsm
Operands: Md
Opcode: 0x0FAE /3
CPU: P3+
Tested by: t3700

IipSTMXCSR:: PROC
    IiModRM /3
    JMP IipLDMXCSR.rm:
 ENDP IipSTMXCSR::

↑ MOVMSKPS: Extract Packed Single-FP Sign Mask
Description: MOVMSKPS
Category: sse1,simdfp,datamov
Operands: Gdqp,Ups
Opcode: 0x0F50 /r
CPU: P3+
Tested by: t3705

IipMOVMSKPS:: PROC
    IiRequire 686,SSE
    IiEmitOpcode 0x0F,0x50
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat r32.xmm, r64.xmm
.r64.xmm:
    IiEmitPrefix REX.W
.r32.xmm:
    RET
 ENDP IipMOVMSKPS::

↑ MOVMSKPD: Extract Packed Double-FP Sign Mask
Description: MOVMSKPD
Category: sse2,pcksclr,datamov
Operands: Gdqp,Upd
Opcode: 0x660F50 /r
CPU: P4+
Tested by: t3705

IipMOVMSKPD:: PROC
    IiRequire 686,SSE2
    IiEmitPrefix OTOGGLE
    JMP IipMOVMSKPS:
 ENDP IipMOVMSKPD::

↑ PSRLDQ: Shift Double Quadword Right Logical
Description: PSRLDQ
Category: sse2,simdint,shift
Operands: Udq,Ib
Opcode: 0x660F73 /3
CPU: P4+
Tested by: t3710

IipPSRLDQ:: PROC
    IiModRM /3
.rm:IiRequire 686,SSE2
    IiEmitPrefix OTOGGLE
    IiEmitOpcode 0x0F,0x73
    IiOpEn M
    IiEmitImm Operand2, BYTE
    IiDispatchFormat xmm.imm
.xmm.imm:
    RET
 ENDP IipPSRLDQ::

↑ PSLLDQ: Shift Double Quadword Left Logical
Description: PSLLDQ
Category: sse2,simdint,shift
Operands: Udq,Ib
Opcode: 0x660F73 /7
CPU: P4+
Tested by: t3710

IipPSLLDQ:: PROC
    IiModRM /7
    JMP IipPSRLDQ.rm:
 ENDP IipPSLLDQ::

↑ CVTTSD2SI: Conv. with Trunc. Scalar Double-FP Value to Signed DW Int
Description: CVTTSD2SI
Category: sse2,pcksclr,conver
Operands: Gdqp,Wsd
Opcode: 0xF20F2C /r
CPU: P4+
Tested by: t3715

IipCVTTSD2SI:: PROC
    IiEmitPrefix REPNE
    MOV CL,0x2C
.pf:IiRequire 686,SSE2
    IiEmitOpcode 0x0F,ECX
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat r32.xmm, r32.mem, r64.xmm, r64.mem
.r64.xmm:
.r64.mem:
    IiEmitPrefix REX.W
    IiEncoding DATA=QWORD
    RET
.r32.xmm:
.r32.mem:
    IiEncoding DATA=DWORD
    RET
 ENDP IipCVTTSD2SI::

↑ CVTSD2SI: Convert Scalar Double-FP Value to DW Integer
Description: CVTSD2SI
Category: sse2,pcksclr,conver
Operands: Gdqp,Wsd
Opcode: 0xF20F2D /r
CPU: P4+
Tested by: t3715

IipCVTSD2SI:: PROC
    IiEmitPrefix REPNE
    MOV CL,0x2D
    JMP IipCVTTSD2SI.pf:
 ENDP IipCVTSD2SI::

↑ CVTSS2SI: Convert Scalar Single-FP Value to DW Integer
Description: CVTSS2SI
Category: sse1,conver
Operands: Gdqp,Wss
Opcode: 0xF30F2D /r
CPU: P3+
Tested by: t3715

IipCVTSS2SI:: PROC
    IiEmitPrefix REPE
    MOV CL,0x2D
    JMP IipCVTTSD2SI.pf:
 ENDP IipCVTSS2SI::

↑ CVTTSS2SI: Convert with Trunc. Scalar Single-FP Value to DW Integer
Description: CVTTSS2SI
Category: sse1,conver
Operands: Gdqp,Wss
Opcode: 0xF30F2C /r
CPU: P3+
Tested by: t3715

IipCVTTSS2SI:: PROC
    IiEmitPrefix REPE
    MOV CL,0x2C
    JMP IipCVTTSD2SI.pf:
 ENDP IipCVTTSS2SI::

↑ CVTSI2SS: Convert DW Integer to Scalar Single-FP Value
Description: CVTSI2SS
Category: sse1,conver
Operands: Vss,Edqp
Opcode: 0xF30F2A /r
CPU: P3+
Tested by: t3720

IipCVTSI2SS:: PROC
    IiEmitPrefix REPE
.pf:IiRequire 686,SSE
    IiDataSize Operand2, StreamingSIMD=ON
    IiEmitOpcode 0x0F,0x2A
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat xmm.r32, xmm.r64, xmm.m32, xmm.m64
.xmm.m64:
.xmm.r64:
    IiEmitPrefix REX.W
.xmm.m32:
.xmm.r32:
    RET
 ENDP IipCVTSI2SS::

↑ CVTSI2SD: Convert DW Integer to Scalar Double-FP Value
Description: CVTSI2SD
Category: sse2,pcksclr,conver
Operands: Vsd,Edqp
Opcode: 0xF20F2A /r
CPU: P4+
Tested by: t3720

IipCVTSI2SD:: PROC
    IiEmitPrefix REPNE
    JMP IipCVTSI2SS.pf:
 ENDP IipCVTSI2SD::

↑ PINSRB: Insert Byte
Description: PINSRB
Category: sse41,simdint,datamov
Operands: Vdq,Mb,Ib | Vdq,Rdqp,Ib
Opcode: 0x660F3A20 /r | 0x660F3A20 /r
CPU: C2++
Documented: D⁴³
Tested by: t3730

IipPINSRB:: PROC
    IiRequire 686,SSE4.1
    IiEncoding DATA=BYTE
    IiEmitPrefix OTOGGLE
    IiEmitOpcode 0x0F,0x3A,0x20
    IiOpEn RM
    IiModRM /r
    IiEmitImm Operand3, BYTE
    IiDispatchFormat xmm.r8.imm, xmm.r16.imm, xmm.r32.imm, xmm.r64.imm, xmm.mem.imm
.xmm.r64.imm:
.xmm.r32.imm:
.xmm.r16.imm:
.xmm.r8.imm:
.xmm.mem.imm:
    RET
 ENDP IipPINSRB::

↑ PINSRD: Insert Dword
Description: PINSRD
Category: sse41,simdint,datamov
Operands: Vdq,Ed,Ib
Opcode: 0x660F3A22 /r
CPU: C2++
Documented: D⁴³
Tested by: t3730

IipPINSRD:: PROC
    IiRequire 686,SSE4.1
    IiEncoding DATA=DWORD
    IiEmitPrefix OTOGGLE
    IiEmitOpcode 0x0F,0x3A,0x22
    IiOpEn RM
    IiModRM /r
    IiEmitImm Operand3, BYTE
    IiDispatchFormat xmm.r32.imm, xmm.r64.imm, xmm.mem.imm
.xmm.r64.imm:
.xmm.r32.imm:
.xmm.mem.imm:
    RET
 ENDP IipPINSRD::

↑ PINSRQ: Insert Qword
Description: PINSRQ
Category: sse41,simdint,datamov
Operands: Vdq,Eqp,Ib
Opcode: 0x660F3A22 /r
CPU: C2++
Documented: D⁴³
Tested by: t3730

IipPINSRQ:: PROC
    IiRequire 686,SSE4.1
    IiEncoding DATA=QWORD
    IiEmitPrefix OTOGGLE, REX.W
    IiEmitOpcode 0x0F,0x3A,0x22
    IiOpEn RM
    IiModRM /r
    IiEmitImm Operand3, BYTE
    IiDispatchFormat xmm.r64.imm, xmm.mem.imm
.xmm.r64.imm:
.xmm.mem.imm:
    RET
 ENDP IipPINSRQ::

↑ MOVUPS: Move Unaligned Packed Single-FP Values
Description: MOVUPS
Category: sse1,simdfp,datamov
Operands: Vps,Wps | Wps,Vps
Opcode: 0x0F10 /r | 0x0F11 /r
CPU: P3+
Tested by: t3735

IipMOVUPS:: PROC
    IiRequire 686,SSE1
    IiAllowModifier CODE
    IiModRM /r
    IiDispatchFormat xmm.mem, mem.xmm, xmm.xmm
.mem.xmm:
    IiEmitOpcode 0x0F,0x11
    IiEncoding CODE=LONG,DATA=OWORD
    IiOpEn MR
    RET
.xmm.xmm:
    JSt [EDI+II.MfgExplicit],iiMfgCODE_LONG,.mem.xmm:
.xmm.mem:
    IiEmitOpcode 0x0F,0x10
    IiEncoding CODE=SHORT,DATA=OWORD
    IiOpEn RM
    RET
 ENDP IipMOVUPS::

↑ MOVAPS: Move Aligned Packed Single-FP Values
Description: MOVAPS
Category: sse1,simdfp,datamov
Operands: Vps,Wps | Wps,Vps
Opcode: 0x0F28 /r | 0x0F29 /r
CPU: P3+
Tested by: t3735

IipMOVAPS:: PROC
    IiRequire 686,SSE1
    IiAllowModifier CODE
    IiModRM /r
    IiDispatchFormat xmm.mem, mem.xmm, xmm.xmm
.mem.xmm:
    IiEmitOpcode 0x0F,0x29
    IiEncoding CODE=LONG,DATA=OWORD
    IiOpEn MR
    RET
.xmm.xmm:
    JSt [EDI+II.MfgExplicit],iiMfgCODE_LONG,.mem.xmm:
.xmm.mem:
    IiEmitOpcode 0x0F,0x28
    IiEncoding CODE=SHORT,DATA=OWORD
    IiOpEn RM
    RET
 ENDP IipMOVAPS::

↑ MOVLPS: Move Low Packed Single-FP Values
Description: MOVLPS
Category: sse1,simdfp,datamov
Operands: Vq,Mq | Mq,Vq
Opcode: 0x0F12 /r | 0x0F13 /r
CPU: P3+
Tested by: t3740

IipMOVLPS:: PROC
    IiEncoding DATA=QWORD
    IiModRM /r
    IiDispatchFormat xmm.mem, mem.xmm
.xmm.mem:
    IiEmitOpcode 0x0F,0x12
    IiOpEn RM
    RET
.mem.xmm:
    IiEmitOpcode 0x0F,0x13
    IiOpEn MR
    RET
 ENDP IipMOVLPS::

↑ MOVHPS: Move High Packed Single-FP Values
Description: MOVHPS
Category: sse1,simdfp,datamov
Operands: Vq,Mq | Mq,Vq
Opcode: 0x0F16 /r | 0x0F17 /r
CPU: P3+
Tested by: t3740

IipMOVHPS:: PROC
    IiEncoding DATA=QWORD
    IiModRM /r
    IiDispatchFormat xmm.mem, mem.xmm
.xmm.mem:
    IiEmitOpcode 0x0F,0x16
    IiOpEn RM
    RET
.mem.xmm:
    IiEmitOpcode 0x0F,0x17
    IiOpEn MR
    RET
 ENDP IipMOVHPS::

↑ MOVHLPS: Move Packed Single-FP Values High to Low
Description: MOVHLPS
Category: sse1,simdfp,datamov
Operands: Vq,Uq
Opcode: 0x0F12 /r
CPU: P3+
Tested by: t3745

IipMOVHLPS:: PROC
    IiEncoding DATA=QWORD
    IiEmitOpcode 0x0F,0x12
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat xmm.xmm
.xmm.xmm:
    RET
 ENDP IipMOVHLPS::

↑ MOVLHPS: Move Packed Single-FP Values Low to High
Description: MOVLHPS
Category: sse1,simdfp,datamov
Operands: Vq,Uq
Opcode: 0x0F16 /r
CPU: P3+
Tested by: t3745

IipMOVLHPS:: PROC
    IiEncoding DATA=QWORD
    IiEmitOpcode 0x0F,0x16
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat xmm.xmm
.xmm.xmm:
    RET
 ENDP IipMOVLHPS::

↑ IipGroupSSE1: IipGroupSSE1 is a common handler for SSE1 instructions in format xmm,xmm/mem encoded with two-byte opcode 0x0F,CL.
Input: CL is the secondary opcode.
EDX has operand types as set by IiAssemble.
EDI is pointer to II structure with parsed operands.
Tested by: t3760 t3765 t3770

IipGroupSSE1:: PROC
     IiEncoding DATA=OWORD
.en: IiEmitOpcode 0x0F,ECX
     IiOpEn RM
     IiModRM /r
     IiDispatchFormat xmm.xmm, xmm.mem
.DW: IiEncoding DATA=DWORD  ; Entry when operand size is DWORD rather than OWORD.
     JMP .en:
.xmm.xmm:
.xmm.mem:
     RET
 ENDP IipGroupSSE1::

↑ UNPCKLPS: Unpack and Interleave Low Packed Single-FP Values
Description: UNPCKLPS
Category: sse1,simdfp,shunpck
Operands: Vps,Wq
Opcode: 0x0F14 /r
CPU: P3+
Tested by: t3760

IipUNPCKLPS:: PROC
    MOV CL,0x14
    JMP IipGroupSSE1:
 ENDP IipUNPCKLPS::

↑ UNPCKHPS: Unpack and Interleave High Packed Single-FP Values
Description: UNPCKHPS
Category: sse1,simdfp,shunpck
Operands: Vps,Wq
Opcode: 0x0F15 /r
CPU: P3+
Tested by: t3760

IipUNPCKHPS:: PROC
    MOV CL,0x15
    JMP IipGroupSSE1:
 ENDP IipUNPCKHPS::

↑ UCOMISS: Unordered Compare Scalar Single-FP Values and Set EFLAGS
Description: UCOMISS
Category: sse1,simdfp,compar
Operands: Vss,Wss
Opcode: 0x0F2E /r
Flags: modified:....Z.PC, defined:....Z.PC
CPU: P3+
Tested by: t3760

IipUCOMISS:: PROC
    MOV CL,0x2E
    JMP IipGroupSSE1.DW:
 ENDP IipUCOMISS::

↑ COMISS: Compare Scalar Ordered Single-FP Values and Set EFLAGS
Description: COMISS
Category: sse1,simdfp,compar
Operands: Vss,Wss
Opcode: 0x0F2F /r
Flags: modified:....Z.PC, defined:....Z.PC
CPU: P3+
Tested by: t3760

IipCOMISS:: PROC
    MOV CL,0x2F
    JMP IipGroupSSE1.DW:
 ENDP IipCOMISS::

↑ SQRTPS: Compute Square Roots of Packed Single-FP Values
Description: SQRTPS
Category: sse1,simdfp,arith
Operands: Vps,Wps
Opcode: 0x0F51 /r
CPU: P3+
Tested by: t3760

IipSQRTPS:: PROC
    MOV CL,0x51
    JMP IipGroupSSE1:
 ENDP IipSQRTPS::

↑ RSQRTPS: Compute Recipr. of Square Roots of Packed Single-FP Values
Description: RSQRTPS
Category: sse1,simdfp,arith
Operands: Vps,Wps
Opcode: 0x0F52 /r
CPU: P3+
Tested by: t3760

IipRSQRTPS:: PROC
    MOV CL,0x52
    JMP IipGroupSSE1:
 ENDP IipRSQRTPS::

↑ RCPPS: Compute Reciprocals of Packed Single-FP Values
Description: RCPPS
Category: sse1,simdfp,arith
Operands: Vps,Wps
Opcode: 0x0F53 /r
CPU: P3+
Tested by: t3760

IipRCPPS:: PROC
    MOV CL,0x53
    JMP IipGroupSSE1:
 ENDP IipRCPPS::

↑ ANDNPS: Bitwise Logical AND NOT of Packed Single-FP Values
Description: ANDNPS
Category: sse1,simdfp,logical
Operands: Vps,Wps
Opcode: 0x0F55 /r
CPU: P3+
Tested by: t3765

IipANDNPS:: PROC
    MOV CL,0x55
    JMP IipGroupSSE1:
 ENDP IipANDNPS::

↑ ANDPS: Bitwise Logical AND of Packed Single-FP Values
Description: ANDPS
Category: sse1,simdfp,logical
Operands: Vps,Wps
Opcode: 0x0F54 /r
CPU: P3+
Tested by: t3765

IipANDPS:: PROC
    MOV CL,0x54
    JMP IipGroupSSE1:
 ENDP IipANDPS::

↑ ORPS: Bitwise Logical OR of Single-FP Values
Description: ORPS
Category: sse1,simdfp,logical
Operands: Vps,Wps
Opcode: 0x0F56 /r
CPU: P3+
Tested by: t3765

IipORPS:: PROC
    MOV CL,0x56
    JMP IipGroupSSE1:
 ENDP IipORPS::

↑ XORPS: Bitwise Logical XOR for Single-FP Values
Description: XORPS
Category: sse1,simdfp,logical
Operands: Vps,Wps
Opcode: 0x0F57 /r
CPU: P3+
Tested by: t3765

IipXORPS:: PROC
    MOV CL,0x57
    JMP IipGroupSSE1:
 ENDP IipXORPS::

↑ ADDPS: Add Packed Single-FP Values
Description: ADDPS
Category: sse1,simdfp,arith
Operands: Vps,Wps
Opcode: 0x0F58 /r
CPU: P3+
Tested by: t3765

IipADDPS:: PROC
    MOV CL,0x58
    JMP IipGroupSSE1:
 ENDP IipADDPS::

↑ MULPS: Multiply Packed Single-FP Values
Description: MULPS
Category: sse1,simdfp,arith
Operands: Vps,Wps
Opcode: 0x0F59 /r
CPU: P3+
Tested by: t3765

IipMULPS:: PROC
    MOV CL,0x59
    JMP IipGroupSSE1:
 ENDP IipMULPS::

↑ CVTPS2PD: Convert Packed Single-FP Values to Double-FP Values
Description: CVTPS2PD
Category: sse2,pcksclr,conver
Operands: Vpd,Wps
Opcode: 0x0F5A /r
CPU: P4+
Tested by: t3770

IipCVTPS2PD:: PROC
    MOV CL,0x5A
    JMP IipGroupSSE1:
 ENDP IipCVTPS2PD::

↑ CVTDQ2PS: Convert Packed DW Integers to Single-FP Values
Description: CVTDQ2PS
Category: sse2,pcksp
Operands: Vps,Wdq
Opcode: 0x0F5B /r
CPU: P4+
Tested by: t3770

IipCVTDQ2PS:: PROC
    MOV CL,0x5B
    JMP IipGroupSSE1:
 ENDP IipCVTDQ2PS::

↑ SUBPS: Subtract Packed Single-FP Values
Description: SUBPS
Category: sse1,simdfp,arith
Operands: Vps,Wps
Opcode: 0x0F5C /r
CPU: P3+
Tested by: t3770

IipSUBPS:: PROC
    MOV CL,0x5C
    JMP IipGroupSSE1:
 ENDP IipSUBPS::

↑ MINPS: Return Minimum Packed Single-FP Values
Description: MINPS
Category: sse1,simdfp,arith
Operands: Vps,Wps
Opcode: 0x0F5D /r
CPU: P3+
Tested by: t3770

IipMINPS:: PROC
    MOV CL,0x5D
    JMP IipGroupSSE1:
 ENDP IipMINPS::

↑ DIVPS: Divide Packed Single-FP Values
Description: DIVPS
Category: sse1,simdfp,arith
Operands: Vps,Wps
Opcode: 0x0F5E /r
CPU: P3+
Tested by: t3770

IipDIVPS:: PROC
    MOV CL,0x5E
    JMP IipGroupSSE1:
 ENDP IipDIVPS::

↑ MAXPS: Return Maximum Packed Single-FP Values
Description: MAXPS
Category: sse1,simdfp,arith
Operands: Vps,Wps
Opcode: 0x0F5F /r
CPU: P3+
Tested by: t3770

IipMAXPS:: PROC
    MOV CL,0x5F
    JMP IipGroupSSE1:
 ENDP IipMAXPS::

↑ MOVHPD: Move High Packed Double-FP Value
Description: MOVHPD
Category: sse2,pcksclr,datamov
Operands: Vq,Mq | Mq,Vq
Opcode: 0x660F16 /r | 0x660F17 /r
CPU: P4+
Tested by: t3750

IipMOVHPD:: PROC
    IiRequire 686,SSE2
    IiEmitPrefix OTOGGLE
    IiEmitOpcode 0x0F
    IiEncoding DATA=QWORD
    IiModRM /r
    IiDispatchFormat xmm.mem, mem.xmm
.xmm.mem:
    IiEmitOpcode 0x16
    IiOpEn RM
    RET
.mem.xmm:
    IiEmitOpcode 0x17
    IiOpEn MR
    RET
 ENDP IipMOVHPD::

↑ MOVLPD: Move Low Packed Double-FP Value
Description: MOVLPD
Category: sse2,pcksclr,datamov
Operands: Vq,Mq | Mq,Vq
Opcode: 0x660F12 /r | 0x660F13 /r
CPU: P4+
Tested by: t3750

IipMOVLPD:: PROC
    IiRequire 686,SSE2
    IiEmitPrefix OTOGGLE
    IiEmitOpcode 0x0F
    IiEncoding DATA=QWORD
    IiModRM /r
    IiDispatchFormat xmm.mem, mem.xmm
.xmm.mem:
    IiEmitOpcode 0x12
    IiOpEn RM
    RET
.mem.xmm:
    IiEmitOpcode 0x13
    IiOpEn MR
    RET
 ENDP IipMOVLPD::

↑ MOVAPD: Move Aligned Packed Double-FP Values
Description: MOVAPD
Category: sse2,pcksclr,datamov
Operands: Vpd,Wpd | Wpd,Vpd
Opcode: 0x660F28 /r | 0x660F29 /r
CPU: P4+
Tested by: t3750

IipMOVAPD:: PROC
    IiRequire 686,SSE2
    IiAllowModifier CODE
    IiEmitPrefix OTOGGLE
    IiEmitOpcode 0x0F
    IiModRM /r
    IiDispatchFormat xmm.mem, mem.xmm, xmm.xmm
.mem.xmm:
    IiEmitOpcode 0x29
    IiEncoding CODE=LONG,DATA=OWORD
    IiOpEn MR
    RET
.xmm.xmm:
    IiDispatchCode LONG=.mem.xmm:
.xmm.mem:
    IiEmitOpcode 0x28
    IiEncoding CODE=SHORT,DATA=OWORD
    IiOpEn RM
    RET
 ENDP IipMOVAPD::

↑ MOVSS: Move Scalar Single-FP Values
Description: MOVSS
Category: sse1,simdfp,datamov
Operands: Vss,Wss | Wss,Vss
Opcode: 0xF30F10 /r | 0xF30F11 /r
CPU: P3+
Tested by: t3750

IipMOVSS:: PROC
    IiAllowModifier CODE
    IiEmitPrefix REPE
    IiEmitOpcode 0x0F
    IiModRM /r
    IiDispatchFormat xmm.mem, mem.xmm, xmm.xmm
.mem.xmm:
    IiEmitOpcode 0x11
    IiEncoding CODE=LONG,DATA=DWORD
    IiOpEn MR
    RET
.xmm.xmm:
    IiDispatchCode LONG=.mem.xmm:
.xmm.mem:
    IiEmitOpcode 0x10
    IiEncoding CODE=SHORT,DATA=DWORD
    IiOpEn RM
    RET
 ENDP IipMOVSS::

↑ MOVUPD: Move Unaligned Packed Double-FP Value
Description: MOVUPD
Category: sse2,pcksclr,datamov
Operands: Vpd,Wpd | Wpd,Vpd
Opcode: 0x660F10 /r | 0x660F11 /r
CPU: P4+
Tested by: t3750

IipMOVUPD:: PROC
    IiRequire 686,SSE2
    IiAllowModifier CODE
    IiEmitPrefix OTOGGLE
    IiEmitOpcode 0x0F
    IiModRM /r
    IiDispatchFormat xmm.mem, mem.xmm, xmm.xmm
.mem.xmm:
    IiEmitOpcode 0x11
    IiEncoding CODE=LONG,DATA=OWORD
    IiOpEn MR
    RET
.xmm.xmm:
    IiDispatchCode LONG=.mem.xmm:
.xmm.mem:
    IiEmitOpcode 0x10
    IiEncoding CODE=SHORT,DATA=OWORD
    IiOpEn RM
    RET
 ENDP IipMOVUPD::

↑ IipGroupSSE4_1: IipGroupSSE4_1 is a common handler for SSE4.1 instructions in format xmm,xmm/mem encoded with prefix and three-byte opcode 0x66,0x0F,0x38,CL.
Input: CL is the tertiary opcode.
EDX has operand types as set by IiAssemble.
EDI is pointer to II structure with parsed operands.
Tested by: t3795 t3800 t3805 t3810

IipGroupSSE4_1:: PROC
     IiRequire 686,SSE4.1
     IiEncoding DATA=OWORD
     IiEmitPrefix OTOGGLE
     IiEmitOpcode 0x0F,0x38,ECX
     IiOpEn RM
     IiModRM /r
     IiDispatchFormat xmm.xmm, xmm.mem
.xmm.xmm:
.xmm.mem:
     RET
 ENDP IipGroupSSE4_1::

↑ PTEST: Logical Compare
Description: PTEST
Category: sse41
Operands: Vdq,Wdq
Opcode: 0x660F3817 /r
Flags: modified:O..SZAPC, defined:O..SZAPC, values:O..S.AP.
CPU: C2++
Documented: D⁴³
Tested by: t3810

IipPTEST:: PROC
    MOV CL,0x17
    JMP IipGroupSSE4_1:
 ENDP IipPTEST::

↑ PMOVSXBW: Packed Move with Sign Extend
Category: sse41,simdint,conver
Operands: Vdq,Mq | Vdq,Udq
Opcode: 0x660F3820 /r | 0x660F3820 /r
CPU: C2++
Documented: D⁴³
Tested by: t3795

IipPMOVSXBW:: PROC
    IiEncoding DATA=QWORD
    MOV CL,0x20
    JMP IipGroupSSE4_1:
 ENDP IipPMOVSXBW::

↑ PMOVSXBD: Packed Move with Sign Extend
Category: sse41,simdint,conver
Operands: Vdq,Md | Vdq,Udq
Opcode: 0x660F3821 /r | 0x660F3821 /r
CPU: C2++
Documented: D⁴³
Tested by: t3795

IipPMOVSXBD:: PROC
    IiEncoding DATA=DWORD
    MOV CL,0x21
    JMP IipGroupSSE4_1:
 ENDP IipPMOVSXBD::

↑ PMOVSXBQ: Packed Move with Sign Extend
Category: sse41,simdint,conver
Operands: Vdq,Mw | Vdq,Udq
Opcode: 0x660F3822 /r | 0x660F3822 /r
CPU: C2++
Documented: D⁴³
Tested by: t3795

IipPMOVSXBQ:: PROC
    IiEncoding DATA=WORD
    MOV CL,0x22
    JMP IipGroupSSE4_1:
 ENDP IipPMOVSXBQ::

↑ PMOVSXWD: Packed Move with Sign Extend
Category: sse41,simdint,conver
Operands: Vdq,Mq | Vdq,Udq
Opcode: 0x660F3823 /r | 0x660F3823 /r
CPU: C2++
Documented: D⁴³
Tested by: t3795

IipPMOVSXWD:: PROC
    IiEncoding DATA=QWORD
    MOV CL,0x23
    JMP IipGroupSSE4_1:
 ENDP IipPMOVSXWD::

↑ PMOVSXWQ: Packed Move with Sign Extend
Category: sse41,simdint,conver
Operands: Vdq,Md | Vdq,Udq
Opcode: 0x660F3824 /r | 0x660F3824 /r
CPU: C2++
Documented: D⁴³
Tested by: t3795

IipPMOVSXWQ:: PROC
    IiEncoding DATA=DWORD
    MOV CL,0x24
    JMP IipGroupSSE4_1:
 ENDP IipPMOVSXWQ::

↑ PMOVSXDQ: Packed Move with Sign Extend
Category: sse41,simdint,conver
Operands: Vdq,Mq | Vdq,Udq
Opcode: 0x660F3825 /r | 0x660F3825 /r
CPU: C2++
Documented: D⁴³
Tested by: t3795

IipPMOVSXDQ:: PROC
    IiEncoding DATA=QWORD
    MOV CL,0x25
    JMP IipGroupSSE4_1:
 ENDP IipPMOVSXDQ::

↑ PMULDQ: Multiply Packed Signed Dword Integers
Description: PMULDQ
Category: sse41,simdint,arith
Operands: Vdq,Wdq
Opcode: 0x660F3828 /r
CPU: C2++
Documented: D⁴³
Tested by: t3810

IipPMULDQ:: PROC
    MOV CL,0x28
    JMP IipGroupSSE4_1:
 ENDP IipPMULDQ::

↑ PCMPEQQ: Compare Packed Qword Data for Equal
Description: PCMPEQQ
Category: sse41,simdint,compar
Operands: Vdq,Wdq
Opcode: 0x660F3829 /r
CPU: C2++
Documented: D⁴³
Tested by: t3810

IipPCMPEQQ:: PROC
    MOV CL,0x29
    JMP IipGroupSSE4_1:
 ENDP IipPCMPEQQ::

↑ PACKUSDW: Pack with Unsigned Saturation
Description: PACKUSDW
Category: sse41,simdint,conver
Operands: Vdq,Wdq
Opcode: 0x660F382B /r
CPU: C2++
Documented: D⁴³
Tested by: t3810

IipPACKUSDW:: PROC
    MOV CL,0x2B
    JMP IipGroupSSE4_1:
 ENDP IipPACKUSDW::

↑ PMOVZXBW: Packed Move with Zero Extend
Category: sse41,simdint,conver
Operands: Vdq,Mq | Vdq,Udq
Opcode: 0x660F3830 /r | 0x660F3830 /r
CPU: C2++
Documented: D⁴³
Tested by: t3800

IipPMOVZXBW:: PROC
    IiEncoding DATA=QWORD
    MOV CL,0x30
    JMP IipGroupSSE4_1:
 ENDP IipPMOVZXBW::

↑ PMOVZXBD: Packed Move with Zero Extend
Category: sse41,simdint,conver
Operands: Vdq,Md | Vdq,Udq
Opcode: 0x660F3831 /r | 0x660F3831 /r
CPU: C2++
Documented: D⁴³
Tested by: t3800

IipPMOVZXBD:: PROC
    IiEncoding DATA=DWORD
    MOV CL,0x31
    JMP IipGroupSSE4_1:
 ENDP IipPMOVZXBD::

↑ PMOVZXBQ: Packed Move with Zero Extend
Category: sse41,simdint,conver
Operands: Vdq,Mw | Vdq,Udq
Opcode: 0x660F3832 /r | 0x660F3832 /r
CPU: C2++
Documented: D⁴³
Tested by: t3800

IipPMOVZXBQ:: PROC
    IiEncoding DATA=WORD
    MOV CL,0x32
    JMP IipGroupSSE4_1:
 ENDP IipPMOVZXBQ::

↑ PMOVZXWD: Packed Move with Zero Extend
Category: sse41,simdint,conver
Operands: Vdq,Mq | Vdq,Udq
Opcode: 0x660F3833 /r | 0x660F3833 /r
CPU: C2++
Documented: D⁴³
Tested by: t3800

IipPMOVZXWD:: PROC
    IiEncoding DATA=QWORD
    MOV CL,0x33
    JMP IipGroupSSE4_1:
 ENDP IipPMOVZXWD::

↑ PMOVZXWQ: Packed Move with Zero Extend
Category: sse41,simdint,conver
Operands: Vdq,Md | Vdq,Udq
Opcode: 0x660F3834 /r | 0x660F3834 /r
CPU: C2++
Documented: D⁴³
Tested by: t3800

IipPMOVZXWQ:: PROC
    IiEncoding DATA=DWORD
    MOV CL,0x34
    JMP IipGroupSSE4_1:
 ENDP IipPMOVZXWQ::

↑ PMOVZXDQ: Packed Move with Zero Extend
Category: sse41,simdint,conver
Operands: Vdq,Mq | Vdq,Udq
Opcode: 0x660F3835 /r | 0x660F3835 /r
CPU: C2++
Documented: D⁴³
Tested by: t3800

IipPMOVZXDQ:: PROC
    IiEncoding DATA=QWORD
    MOV CL,0x35
    JMP IipGroupSSE4_1:
 ENDP IipPMOVZXDQ::

↑ PCMPGTQ: Compare Packed Qword Data for Greater Than
Description: PCMPGTQ
Category: sse42,simdint,compar
Operands: Vdq,Wdq
Opcode: 0x660F3837 /r
CPU: C2++
Documented: D⁴³
Tested by: t3810

IipPCMPGTQ:: PROC
    IiRequire SSE4.2
    MOV CL,0x37
    JMP IipGroupSSE4_1:
 ENDP IipPCMPGTQ::

↑ PMINSB: Minimum of Packed Signed Byte Integers
Description: PMINSB
Category: sse41,simdint,compar
Operands: Vdq,Wdq
Opcode: 0x660F3838 /r
CPU: C2++
Documented: D⁴³
Tested by: t3805

IipPMINSB:: PROC
    MOV CL,0x38
    JMP IipGroupSSE4_1:
 ENDP IipPMINSB::

↑ PMINSD: Minimum of Packed Signed Dword Integers
Description: PMINSD
Category: sse41,simdint,compar
Operands: Vdq,Wdq
Opcode: 0x660F3839 /r
CPU: C2++
Documented: D⁴³
Tested by: t3805

IipPMINSD:: PROC
    MOV CL,0x39
    JMP IipGroupSSE4_1:
 ENDP IipPMINSD::

↑ PMINUW: Minimum of Packed Unsigned Word Integers
Description: PMINUW
Category: sse41,simdint,compar
Operands: Vdq,Wdq
Opcode: 0x660F383A /r
CPU: C2++
Documented: D⁴³
Tested by: t3805

IipPMINUW:: PROC
    MOV CL,0x3A
    JMP IipGroupSSE4_1:
 ENDP IipPMINUW::

↑ PMINUD: Minimum of Packed Unsigned Dword Integers
Description: PMINUD
Category: sse41,simdint,compar
Operands: Vdq,Wdq
Opcode: 0x660F383B /r
CPU: C2++
Documented: D⁴³
Tested by: t3805

IipPMINUD:: PROC
    MOV CL,0x3B
    JMP IipGroupSSE4_1:
 ENDP IipPMINUD::

↑ PMAXSB: Maximum of Packed Signed Byte Integers
Description: PMAXSB
Category: sse41,simdint,compar
Operands: Vdq,Wdq
Opcode: 0x660F383C /r
CPU: C2++
Documented: D⁴³
Tested by: t3805

IipPMAXSB:: PROC
    MOV CL,0x3C
    JMP IipGroupSSE4_1:
 ENDP IipPMAXSB::

↑ PMAXSD: Maximum of Packed Signed Dword Integers
Description: PMAXSD
Category: sse41,simdint,compar
Operands: Vdq,Wdq
Opcode: 0x660F383D /r
CPU: C2++
Documented: D⁴³
Tested by: t3805

IipPMAXSD:: PROC
    MOV CL,0x3D
    JMP IipGroupSSE4_1:
 ENDP IipPMAXSD::

↑ PMAXUW: Maximum of Packed Unsigned Word Integers
Description: PMAXUW
Category: sse41,simdint,compar
Operands: Vdq,Wdq
Opcode: 0x660F383E /r
CPU: C2++
Documented: D⁴³
Tested by: t3805

IipPMAXUW:: PROC
    MOV CL,0x3E
    JMP IipGroupSSE4_1:
 ENDP IipPMAXUW::

↑ PMAXUD: Maximum of Packed Unsigned Dword Integers
Description: PMAXUD
Category: sse41,simdint,compar
Operands: Vdq,Wdq
Opcode: 0x660F383F /r
CPU: C2++
Documented: D⁴³
Tested by: t3805

IipPMAXUD:: PROC
    MOV CL,0x3F
    JMP IipGroupSSE4_1:
 ENDP IipPMAXUD::

↑ PMULLD: Multiply Packed Signed Dword Integers and Store Low Result
Description: PMULLD
Category: sse41,simdint,arith
Operands: Vdq,Wdq
Opcode: 0x660F3840 /r
CPU: C2++
Documented: D⁴³
Tested by: t3810

IipPMULLD:: PROC
    MOV CL,0x40
    JMP IipGroupSSE4_1:
 ENDP IipPMULLD::

↑ PHMINPOSUW: Packed Horizontal Word Minimum
Description: PHMINPOSUW
Category: sse41,simdint,compar
Operands: Vdq,Wdq
Opcode: 0x660F3841 /r
CPU: C2++
Documented: D⁴³
Tested by: t3810

IipPHMINPOSUW:: PROC
    MOV CL,0x41
    JMP IipGroupSSE4_1:
 ENDP IipPHMINPOSUW::

↑ IipGroupSSE: IipGroupSSE is a common handler for SSE1, SSE2 or SSE3 instructions in format xmm, xmm/mem encoded with prefix and two-byte opcode Pfx,0x0F,CL.
Input: EAX is iiMfgDATA_Mask encoding of operand size.
CL is secondary opcode.
EDX has operand types as set by IiAssemble.
EDI is pointer to II structure with parsed operands.
Tested by: t3830 t3835 t3840 t3845 t3850 t3855 t3860

IipGroupSSE:: PROC
    IiEncoding EAX
    IiEmitOpcode 0x0F,ECX
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat xmm.xmm, xmm.mem
.xmm.xmm:
.xmm.mem:
    RET
; Procedure entries which specify required SSE level and prefix.
.3.66:IiRequire SSE3
.2.66:IiRequire SSE2
.1.66:IiEmitPrefix OTOGGLE
      JMP IipGroupSSE:
.3.F2:IiRequire SSE3
.2.F2:IiRequire SSE2
.1.F2:IiEmitPrefix REPNE
      JMP IipGroupSSE:
.3.F3:IiRequire SSE3
.2.F3:IiRequire SSE2
.1.F3:IiEmitPrefix REPE
      JMP IipGroupSSE:
 ENDP IipGroupSSE::

↑ UNPCKLPD: Unpack and Interleave Low Packed Double-FP Values
Description: UNPCKLPD
Category: sse2,pcksclr,shunpck
Operands: Vpd,Wpd
Opcode: 0x660F14 /r
CPU: P4+
Tested by: t3855

IipUNPCKLPD:: PROC
    MOV EAX,iiMfgDATA_OWORD
    MOV CL,0x14
    JMP IipGroupSSE.2.66:
 ENDP IipUNPCKLPD::

↑ UNPCKHPD: Unpack and Interleave High Packed Double-FP Values
Description: UNPCKHPD
Category: sse2,pcksclr,shunpck
Operands: Vpd,Wpd
Opcode: 0x660F15 /r
CPU: P4+
Tested by: t3855

IipUNPCKHPD:: PROC
    MOV EAX,iiMfgDATA_OWORD
    MOV CL,0x15
    JMP IipGroupSSE.2.66:
 ENDP IipUNPCKHPD::

↑ UCOMISD: Unordered Compare Scalar Double-FP Values and Set EFLAGS
Description: UCOMISD
Category: sse2,pcksclr,compar
Operands: Vsd,Wsd
Opcode: 0x660F2E /r
Flags: modified:....Z.PC, defined:....Z.PC
CPU: P4+
Tested by: t3855

IipUCOMISD:: PROC
    MOV EAX,iiMfgDATA_QWORD
    MOV CL,0x2E
    JMP IipGroupSSE.2.66:
 ENDP IipUCOMISD::

↑ COMISD: Compare Scalar Ordered Double-FP Values and Set EFLAGS
Description: COMISD
Category: sse2,pcksclr,compar
Operands: Vsd,Wsd
Opcode: 0x660F2F /r
Flags: modified:....Z.PC, defined:....Z.PC
CPU: P4+
Tested by: t3855

IipCOMISD:: PROC
    MOV EAX,iiMfgDATA_OWORD
    MOV CL,0x2F
    JMP IipGroupSSE.2.66:
 ENDP IipCOMISD::

↑ SQRTPD: Compute Square Roots of Packed Double-FP Values
Description: SQRTPD
Category: sse2,pcksclr,arith
Operands: Vpd,Wpd
Opcode: 0x660F51 /r
CPU: P4+
Tested by: t3850

IipSQRTPD:: PROC
    MOV EAX,iiMfgDATA_OWORD
    MOV CL,0x51
    JMP IipGroupSSE.2.66:
 ENDP IipSQRTPD::

↑ ANDPD: Bitwise Logical AND of Packed Double-FP Values
Description: ANDPD
Category: sse2,pcksclr,logical
Operands: Vpd,Wpd
Opcode: 0x660F54 /r
CPU: P4+
Tested by: t3840

IipANDPD:: PROC
    MOV EAX,iiMfgDATA_OWORD
    MOV CL,0x54
    JMP IipGroupSSE.2.66:
 ENDP IipANDPD::

↑ ANDNPD: Bitwise Logical AND NOT of Packed Double-FP Values
Description: ANDNPD
Category: sse2,pcksclr,logical
Operands: Vpd,Wpd
Opcode: 0x660F55 /r
CPU: P4+
Tested by: t3840

IipANDNPD:: PROC
    MOV EAX,iiMfgDATA_OWORD
    MOV CL,0x55
    JMP IipGroupSSE.2.66:
 ENDP IipANDNPD::

↑ ORPD: Bitwise Logical OR of Double-FP Values
Description: ORPD
Category: sse2,pcksclr,logical
Operands: Vpd,Wpd
Opcode: 0x660F56 /r
CPU: P4+
Tested by: t3840

IipORPD:: PROC
    MOV EAX,iiMfgDATA_OWORD
    MOV CL,0x56
    JMP IipGroupSSE.2.66:
 ENDP IipORPD::

↑ XORPD: Bitwise Logical XOR for Double-FP Values
Description: XORPD
Category: sse2,pcksclr,logical
Operands: Vpd,Wpd
Opcode: 0x660F57 /r
CPU: P4+
Tested by: t3840

IipXORPD:: PROC
    MOV EAX,iiMfgDATA_OWORD
    MOV CL,0x57
    JMP IipGroupSSE.2.66:
 ENDP IipXORPD::

↑ ADDPD: Add Packed Double-FP Values
Description: ADDPD
Category: sse2,pcksclr,arith
Operands: Vpd,Wpd
Opcode: 0x660F58 /r
CPU: P4+
Tested by: t3840

IipADDPD:: PROC
    MOV EAX,iiMfgDATA_OWORD
    MOV CL,0x58
    JMP IipGroupSSE.2.66:
 ENDP IipADDPD::

↑ MULPD: Multiply Packed Double-FP Values
Description: MULPD
Category: sse2,pcksclr,arith
Operands: Vpd,Wpd
Opcode: 0x660F59 /r
CPU: P4+
Tested by: t3850

IipMULPD:: PROC
    MOV EAX,iiMfgDATA_OWORD
    MOV CL,0x59
    JMP IipGroupSSE.2.66:
 ENDP IipMULPD::

↑ CVTPD2PS: Convert Packed Double-FP Values to Single-FP Values
Description: CVTPD2PS
Category: sse2,pcksclr,conver
Operands: Vps,Wpd
Opcode: 0x660F5A /r
CPU: P4+
Tested by: t3845

IipCVTPD2PS:: PROC
    MOV EAX,iiMfgDATA_OWORD
    MOV CL,0x5A
    JMP IipGroupSSE.2.66:
 ENDP IipCVTPD2PS::

↑ CVTPS2DQ: Convert Packed Single-FP Values to DW Integers
Description: CVTPS2DQ
Category: sse2,pcksp
Operands: Vdq,Wps
Opcode: 0x660F5B /r
CPU: P4+
Tested by: t3845

IipCVTPS2DQ:: PROC
    MOV EAX,iiMfgDATA_OWORD
    MOV CL,0x5B
    JMP IipGroupSSE.2.66:
 ENDP IipCVTPS2DQ::

↑ SUBPD: Subtract Packed Double-FP Values
Description: SUBPD
Category: sse2,pcksclr,arith
Operands: Vpd,Wpd
Opcode: 0x660F5C /r
CPU: P4+
Tested by: t3855

IipSUBPD:: PROC
    MOV EAX,iiMfgDATA_OWORD
    MOV CL,0x5C
    JMP IipGroupSSE.2.66:
 ENDP IipSUBPD::

↑ MINPD: Return Minimum Packed Double-FP Values
Description: MINPD
Category: sse2,pcksclr,arith
Operands: Vpd,Wpd
Opcode: 0x660F5D /r
CPU: P4+
Tested by: t3850

IipMINPD:: PROC
    MOV EAX,iiMfgDATA_OWORD
    MOV CL,0x5D
    JMP IipGroupSSE.2.66:
 ENDP IipMINPD::

↑ DIVPD: Divide Packed Double-FP Values
Description: DIVPD
Category: sse2,pcksclr,arith
Operands: Vpd,Wpd
Opcode: 0x660F5E /r
CPU: P4+
Tested by: t3840

IipDIVPD:: PROC
    MOV EAX,iiMfgDATA_OWORD
    MOV CL,0x5E
    JMP IipGroupSSE.2.66:
 ENDP IipDIVPD::

↑ MAXPD: Return Maximum Packed Double-FP Values
Description: MAXPD
Category: sse2,pcksclr,arith
Operands: Vpd,Wpd
Opcode: 0x660F5F /r
CPU: P4+
Tested by: t3850

IipMAXPD:: PROC
    MOV EAX,iiMfgDATA_OWORD
    MOV CL,0x5F
    JMP IipGroupSSE.2.66:
 ENDP IipMAXPD::

↑ PUNPCKLQDQ: Unpack Low Data
Description: PUNPCKLQDQ
Category: sse2,simdint,shunpck
Operands: Vdq,Wdq
Opcode: 0x660F6C /r
CPU: P4+
Tested by: t3855

IipPUNPCKLQDQ:: PROC
    MOV EAX,iiMfgDATA_OWORD
    MOV CL,0x6C
    JMP IipGroupSSE.2.66:
 ENDP IipPUNPCKLQDQ::

↑ PUNPCKHQDQ: Unpack High Data
Description: PUNPCKHQDQ
Category: sse2,simdint,shunpck
Operands: Vdq,Wdq
Opcode: 0x660F6D /r
CPU: P4+
Tested by: t3855

IipPUNPCKHQDQ:: PROC
    MOV EAX,iiMfgDATA_OWORD
    MOV CL,0x6D
    JMP IipGroupSSE.2.66:
 ENDP IipPUNPCKHQDQ::

↑ HADDPD: Packed Double-FP Horizontal Add
Description: HADDPD
Category: sse3,simdfp,arith
Operands: Vpd,Wpd
Opcode: 0x660F7C /r
CPU: P4++
Tested by: t3860

IipHADDPD:: PROC
    MOV EAX,iiMfgDATA_OWORD
    MOV CL,0x7C
    JMP IipGroupSSE.3.66:
 ENDP IipHADDPD::

↑ HSUBPD: Packed Double-FP Horizontal Subtract
Description: HSUBPD
Category: sse3,simdfp,arith
Operands: Vpd,Wpd
Opcode: 0x660F7D /r
CPU: P4++
Tested by: t3860

IipHSUBPD:: PROC
    MOV EAX,iiMfgDATA_OWORD
    MOV CL,0x7D
    JMP IipGroupSSE.3.66:
 ENDP IipHSUBPD::

↑ ADDSUBPD: Packed Double-FP Add/Subtract
Description: ADDSUBPD
Category: sse3,simdfp,arith
Operands: Vpd,Wpd
Opcode: 0x660FD0 /r
CPU: P4++
Tested by: t3860

IipADDSUBPD:: PROC
    MOV EAX,iiMfgDATA_OWORD
    MOV CL,0xD0
    JMP IipGroupSSE.3.66:
 ENDP IipADDSUBPD::

↑ CVTTPD2DQ: Convert with Trunc. Packed Double-FP Values to DW Integers
Description: CVTTPD2DQ
Category: sse2,pcksclr,conver
Operands: Vdq,Wpd
Opcode: 0x660FE6 /r
CPU: P4+
Tested by: t3845

IipCVTTPD2DQ:: PROC
    MOV EAX,iiMfgDATA_OWORD
    MOV CL,0xE6
    JMP IipGroupSSE.2.66:
 ENDP IipCVTTPD2DQ::

↑ MOVDDUP: Move One Double-FP and Duplicate
Description: MOVDDUP
Category: sse3,simdfp,datamov
Operands: Vq,Wq
Opcode: 0xF20F12 /r
CPU: P4++
Tested by: t3860

IipMOVDDUP:: PROC
    MOV EAX,iiMfgDATA_QWORD+iiMfgDATA_OWORD
    MOV CL,0x12
    JMP IipGroupSSE.3.F2:
 ENDP IipMOVDDUP::

↑ SQRTSD: Compute Square Root of Scalar Double-FP Value
Description: SQRTSD
Category: sse2,pcksclr,arith
Operands: Vsd,Wsd
Opcode: 0xF20F51 /r
CPU: P4+
Tested by: t3850

IipSQRTSD:: PROC
    MOV EAX,iiMfgDATA_QWORD
    MOV CL,0x51
    JMP IipGroupSSE.2.F2:
 ENDP IipSQRTSD::

↑ ADDSD: Add Scalar Double-FP Values
Description: ADDSD
Category: sse2,pcksclr,arith
Operands: Vsd,Wsd
Opcode: 0xF20F58 /r
CPU: P4+
Tested by: t3840

IipADDSD:: PROC
    MOV EAX,iiMfgDATA_QWORD
    MOV CL,0x58
    JMP IipGroupSSE.2.F2:
 ENDP IipADDSD::

↑ MULSD: Multiply Scalar Double-FP Values
Description: MULSD
Category: sse2,pcksclr,arith
Operands: Vsd,Wsd
Opcode: 0xF20F59 /r
CPU: P4+
Tested by: t3850

IipMULSD:: PROC
    MOV EAX,iiMfgDATA_QWORD
    MOV CL,0x59
    JMP IipGroupSSE.2.F2:
 ENDP IipMULSD::

↑ CVTSD2SS: Convert Scalar Double-FP Value to Scalar Single-FP Value
Description: CVTSD2SS
Category: sse2,pcksclr,conver
Operands: Vss,Wsd
Opcode: 0xF20F5A /r
CPU: P4+
Tested by: t3845

IipCVTSD2SS:: PROC
    MOV EAX,iiMfgDATA_QWORD+iiMfgDATA_DWORD
    MOV CL,0x5A
    JMP IipGroupSSE.2.F2:
 ENDP IipCVTSD2SS::

↑ SUBSD: Subtract Scalar Double-FP Values
Description: SUBSD
Category: sse2,pcksclr,arith
Operands: Vsd,Wsd
Opcode: 0xF20F5C /r
CPU: P4+
Tested by: t3855

IipSUBSD:: PROC
    MOV EAX,iiMfgDATA_QWORD
    MOV CL,0x5C
    JMP IipGroupSSE.2.F2:
 ENDP IipSUBSD::

↑ MINSD: Return Minimum Scalar Double-FP Value
Description: MINSD
Category: sse2,pcksclr,arith
Operands: Vsd,Wsd
Opcode: 0xF20F5D /r
CPU: P4+
Tested by: t3850

IipMINSD:: PROC
    MOV EAX,iiMfgDATA_QWORD
    MOV CL,0x5D
    JMP IipGroupSSE.2.F2:
 ENDP IipMINSD::

↑ DIVSD: Divide Scalar Double-FP Values
Description: DIVSD
Category: sse2,pcksclr,arith
Operands: Vsd,Wsd
Opcode: 0xF20F5E /r
CPU: P4+
Tested by: t3840

IipDIVSD:: PROC
    MOV EAX,iiMfgDATA_QWORD
    MOV CL,0x5E
    JMP IipGroupSSE.2.F2:
 ENDP IipDIVSD::

↑ MAXSD: Return Maximum Scalar Double-FP Value
Description: MAXSD
Category: sse2,pcksclr,arith
Operands: Vsd,Wsd
Opcode: 0xF20F5F /r
CPU: P4+
Tested by: t3850

IipMAXSD:: PROC
    MOV EAX,iiMfgDATA_QWORD
    MOV CL,0x5F
    JMP IipGroupSSE.2.F2:
 ENDP IipMAXSD::

↑ HADDPS: Packed Single-FP Horizontal Add
Description: HADDPS
Category: sse3,simdfp,arith
Operands: Vps,Wps
Opcode: 0xF20F7C /r
CPU: P4++
Tested by: t3860

IipHADDPS:: PROC
    MOV EAX,iiMfgDATA_QWORD+iiMfgDATA_OWORD
    MOV CL,0x7C
    JMP IipGroupSSE.3.F2:
 ENDP IipHADDPS::

↑ HSUBPS: Packed Single-FP Horizontal Subtract
Description: HSUBPS
Category: sse3,simdfp,arith
Operands: Vps,Wps
Opcode: 0xF20F7D /r
CPU: P4++
Tested by: t3860

IipHSUBPS:: PROC
    MOV EAX,iiMfgDATA_QWORD+iiMfgDATA_OWORD
    MOV CL,0x7D
    JMP IipGroupSSE.3.F2:
 ENDP IipHSUBPS::

↑ ADDSUBPS: Packed Single-FP Add/Subtract
Description: ADDSUBPS
Category: sse3,simdfp,arith
Operands: Vps,Wps
Opcode: 0xF20FD0 /r
CPU: P4++
Tested by: t3830

IipADDSUBPS:: PROC
    MOV EAX,iiMfgDATA_QWORD
    MOV CL,0xD0
    JMP IipGroupSSE.3.F2:
 ENDP IipADDSUBPS::

↑ CVTPD2DQ: Convert Packed Double-FP Values to DW Integers
Description: CVTPD2DQ
Category: sse2,pcksclr,conver
Operands: Vdq,Wpd
Opcode: 0xF20FE6 /r
CPU: P4+
Tested by: t3845

IipCVTPD2DQ:: PROC
    MOV EAX,iiMfgDATA_QWORD
    MOV CL,0xE6
    JMP IipGroupSSE.2.F2:
 ENDP IipCVTPD2DQ::

↑ MOVSLDUP: Move Packed Single-FP Low and Duplicate
Description: MOVSLDUP
Category: sse3,simdfp,datamov
Operands: Vq,Wq
Opcode: 0xF30F12 /r
CPU: P4++
Tested by: t3860

IipMOVSLDUP:: PROC
    MOV EAX,iiMfgDATA_OWORD
    MOV CL,0x12
    JMP IipGroupSSE.3.F3:
 ENDP IipMOVSLDUP::

↑ MOVSHDUP: Move Packed Single-FP High and Duplicate
Description: MOVSHDUP
Category: sse3,simdfp,datamov
Operands: Vq,Wq
Opcode: 0xF30F16 /r
CPU: P4++
Tested by: t3860

IipMOVSHDUP:: PROC
    MOV EAX,iiMfgDATA_OWORD
    MOV CL,0x16
    JMP IipGroupSSE.3.F3:
 ENDP IipMOVSHDUP::

↑ SQRTSS: Compute Square Root of Scalar Single-FP Value
Description: SQRTSS
Category: sse1,simdfp,arith
Operands: Vss,Wss
Opcode: 0xF30F51 /r
CPU: P3+
Tested by: t3830

IipSQRTSS:: PROC
    MOV EAX,iiMfgDATA_DWORD
    MOV CL,0x51
    JMP IipGroupSSE.1.F3:
 ENDP IipSQRTSS::

↑ RSQRTSS: Compute Recipr. of Square Root of Scalar Single-FP Value
Description: RSQRTSS
Category: sse1,simdfp,arith
Operands: Vss,Wss
Opcode: 0xF30F52 /r
CPU: P3+
Tested by: t3835

IipRSQRTSS:: PROC
    MOV EAX,iiMfgDATA_DWORD
    MOV CL,0x52
    JMP IipGroupSSE.1.F3:
 ENDP IipRSQRTSS::

↑ RCPSS: Compute Reciprocal of Scalar Single-FP Values
Description: RCPSS
Category: sse1,simdfp,arith
Operands: Vss,Wss
Opcode: 0xF30F53 /r
CPU: P3+
Tested by: t3835

IipRCPSS:: PROC
    MOV EAX,iiMfgDATA_DWORD
    MOV CL,0x53
    JMP IipGroupSSE.1.F3:
 ENDP IipRCPSS::

↑ ADDSS: Add Scalar Single-FP Values
Description: ADDSS
Category: sse1,simdfp,arith
Operands: Vss,Wss
Opcode: 0xF30F58 /r
CPU: P3+
Tested by: t3830

IipADDSS:: PROC
    MOV EAX,iiMfgDATA_DWORD
    MOV CL,0x58
    JMP IipGroupSSE.1.F3:
 ENDP IipADDSS::

↑ MULSS: Multiply Scalar Single-FP Value
Description: MULSS
Category: sse1,simdfp,arith
Operands: Vss,Wss
Opcode: 0xF30F59 /r
CPU: P3+
Tested by: t3835

IipMULSS:: PROC
    MOV EAX,iiMfgDATA_DWORD
    MOV CL,0x59
    JMP IipGroupSSE.1.F3:
 ENDP IipMULSS::

↑ CVTSS2SD: Convert Scalar Single-FP Value to Scalar Double-FP Value
Description: CVTSS2SD
Category: sse2,pcksclr,conver
Operands: Vsd,Wss
Opcode: 0xF30F5A /r
CPU: P4+
Tested by: t3845

IipCVTSS2SD:: PROC
    MOV EAX,iiMfgDATA_DWORD+iiMfgDATA_QWORD
    MOV CL,0x5A
    JMP IipGroupSSE.2.F3:
 ENDP IipCVTSS2SD::

↑ CVTTPS2DQ: Convert with Trunc. Packed Single-FP Values to DW Integers
Description: CVTTPS2DQ
Category: sse2,pcksp
Operands: Vdq,Wps
Opcode: 0xF30F5B /r
CPU: P4+
Tested by: t3845

IipCVTTPS2DQ:: PROC
    MOV EAX,iiMfgDATA_OWORD
    MOV CL,0x5B
    JMP IipGroupSSE.2.F3:
 ENDP IipCVTTPS2DQ::

↑ SUBSS: Subtract Scalar Single-FP Values
Description: SUBSS
Category: sse1,simdfp,arith
Operands: Vss,Wss
Opcode: 0xF30F5C /r
CPU: P3+
Tested by: t3830

IipSUBSS:: PROC
    MOV EAX,iiMfgDATA_DWORD
    MOV CL,0x5C
    JMP IipGroupSSE.1.F3:
 ENDP IipSUBSS::

↑ MINSS: Return Minimum Scalar Single-FP Value
Description: MINSS
Category: sse1,simdfp,arith
Operands: Vss,Wss
Opcode: 0xF30F5D /r
CPU: P3+
Tested by: t3835

IipMINSS:: PROC
    MOV EAX,iiMfgDATA_DWORD
    MOV CL,0x5D
    JMP IipGroupSSE.1.F3:
 ENDP IipMINSS::

↑ DIVSS: Divide Scalar Single-FP Values
Description: DIVSS
Category: sse1,simdfp,arith
Operands: Vss,Wss
Opcode: 0xF30F5E /r
CPU: P3+
Tested by: t3830

IipDIVSS:: PROC
    MOV EAX,iiMfgDATA_DWORD
    MOV CL,0x5E
    JMP IipGroupSSE.1.F3:
 ENDP IipDIVSS::

↑ MAXSS: Return Maximum Scalar Single-FP Value
Description: MAXSS
Category: sse1,simdfp,arith
Operands: Vss,Wss
Opcode: 0xF30F5F /r
CPU: P3+
Tested by: t3835

IipMAXSS:: PROC
    MOV EAX,iiMfgDATA_DWORD
    MOV CL,0x5F
    JMP IipGroupSSE.1.F3:
 ENDP IipMAXSS::

↑ CVTDQ2PD: Convert Packed DW Integers to Double-FP Values
Description: CVTDQ2PD
Category: sse2,pcksclr,conver
Operands: Vpd,Wdq
Opcode: 0xF30FE6 /r
CPU: P4+
Tested by: t3845

IipCVTDQ2PD:: PROC
    MOV EAX,iiMfgDATA_QWORD+iiMfgDATA_OWORD
    MOV CL,0xE6
    JMP IipGroupSSE.2.F3:
 ENDP IipCVTDQ2PD::

↑ IipGroupSSE4: IipGroupSSE4 is a common handler for SSE4 instructions in format xmm,xmm/mem,imm8 encoded with prefix and three-byte opcode 0x66,0x0F,0x3A,CL.
Input: CL is the tertiary opcode.
EDX has operand types as set by IiAssemble.
EDI is pointer to II structure with parsed operands.
Tested by: t3815 t3820

IipGroupSSE4:: PROC
     IiRequire 686,SSE4.1
     IiEncoding DATA=OWORD
     IiEmitPrefix OTOGGLE
     IiEmitOpcode 0x0F,0x3A,ECX
     IiOpEn RM
     IiModRM /r
     IiEmitImm Operand3, BYTE
     IiDispatchFormat xmm.xmm.imm, xmm.mem.imm
.xmm.xmm.imm:
.xmm.mem.imm:
     RET
 ENDP IipGroupSSE4::

↑ ROUNDPS: Round Packed Single-FP Values
Description: ROUNDPS
Category: sse41,simdfp,conver
Operands: Vps,Wps,Ib
Opcode: 0x660F3A08 /r
CPU: C2++
Documented: D⁴³
Tested by: t3815

IipROUNDPS:: PROC
    MOV CL,0x08
    JMP IipGroupSSE4:
 ENDP IipROUNDPS::

↑ ROUNDPD: Round Packed Double-FP Values
Description: ROUNDPD
Category: sse41,simdfp,conver
Operands: Vps,Wpd,Ib
Opcode: 0x660F3A09 /r
CPU: C2++
Documented: D⁴³
Tested by: t3815

IipROUNDPD:: PROC
    MOV CL,0x09
    JMP IipGroupSSE4:
 ENDP IipROUNDPD::

↑ ROUNDSS: Round Scalar Single-FP Values
Description: ROUNDSS
Category: sse41,simdfp,conver
Operands: Vss,Wss,Ib
Opcode: 0x660F3A0A /r
CPU: C2++
Documented: D⁴³
Tested by: t3815

IipROUNDSS:: PROC
    MOV CL,0x0A
    JMP IipGroupSSE4:
 ENDP IipROUNDSS::

↑ ROUNDSD: Round Scalar Double-FP Values
Description: ROUNDSD
Category: sse41,simdfp,conver
Operands: Vsd,Wsd,Ib
Opcode: 0x660F3A0B /r
CPU: C2++
Documented: D⁴³
Tested by: t3815

IipROUNDSD:: PROC
    MOV CL,0x0B
    JMP IipGroupSSE4:
 ENDP IipROUNDSD::

↑ BLENDPS: Blend Packed Single-FP Values
Description: BLENDPS
Category: sse41,simdfp,datamov
Operands: Vps,Wps,Ib
Opcode: 0x660F3A0C /r
CPU: C2++
Documented: D⁴³
Tested by: t3815

IipBLENDPS:: PROC
    MOV CL,0x0C
    JMP IipGroupSSE4:
 ENDP IipBLENDPS::

↑ BLENDPD: Blend Packed Double-FP Values
Description: BLENDPD
Category: sse41,simdfp,datamov
Operands: Vpd,Wpd,Ib
Opcode: 0x660F3A0D /r
CPU: C2++
Documented: D⁴³
Tested by: t3815

IipBLENDPD:: PROC
    MOV CL,0x0D
    JMP IipGroupSSE4:
 ENDP IipBLENDPD::

↑ PBLENDW: Blend Packed Words
Description: PBLENDW
Category: sse41,simdint,datamov
Operands: Vdq,Wdq,Ib
Opcode: 0x660F3A0E /r
CPU: C2++
Documented: D⁴³
Tested by: t3815

IipPBLENDW:: PROC
    MOV CL,0x0E
    JMP IipGroupSSE4:
 ENDP IipPBLENDW::

↑ INSERTPS: Insert Packed Single-FP Value
Description: INSERTPS
Category: sse41,simdfp,datamov
Operands: Vps,Ups,Ib | Vps,Md,Ib
Opcode: 0x660F3A21 /r | 0x660F3A21 /r
CPU: C2++
Documented: D⁴³
Tested by: t3815

IipINSERTPS:: PROC
    MOV CL,0x21
    JMP IipGroupSSE4:
 ENDP IipINSERTPS::

↑ DPPS: Dot Product of Packed Single-FP Values
Description: DPPS
Category: sse41,simdfp,arith
Operands: Vps,Wps
Opcode: 0x660F3A40 /r
CPU: C2++
Documented: D⁴³
Tested by: t3820

IipDPPS:: PROC
    MOV CL,0x40
    JMP IipGroupSSE4:
 ENDP IipDPPS::

↑ DPPD: Dot Product of Packed Double-FP Values
Description: DPPD
Category: sse41,simdfp,arith
Operands: Vpd,Wpd
Opcode: 0x660F3A41 /r
CPU: C2++
Documented: D⁴³
Tested by: t3820

IipDPPD:: PROC
    MOV CL,0x41
    JMP IipGroupSSE4:
 ENDP IipDPPD::

↑ MPSADBW: Compute Multiple Packed Sums of Absolute Difference
Description: MPSADBW
Category: sse41,simdint,arith
Operands: Vdq,Wdq,Ib
Opcode: 0x660F3A42 /r
CPU: C2++
Documented: D⁴³
Tested by: t3820

IipMPSADBW:: PROC
    MOV CL,0x42
    JMP IipGroupSSE4:
 ENDP IipMPSADBW::

↑ PCMPESTRM: Packed Compare Explicit Length Strings, Return Mask
Modifier DATA=D | DATA=Q specifies if the implicit length registers are EAX,EDX | RAX,RDX.
Description: PCMPESTRM
Category: sse42,strtxt
Operands: XMM0,Vdq,Wdq,...
Opcode: 0x660F3A60 /r
Flags: modified:O..SZAPC, defined:O..SZAPC, values:.....AP.
CPU: C2++
Documented: D⁴³
Tested by: t3820

IipPCMPESTRM:: PROC
     MOV CL,0x60
.op: IiRequire SSE4.2
     IiAllowModifier DATA
     JSt [EDI+II.MfgExplicit],iiMfgDATA_QWORD,.r64:
     IiEncoding DATA=DWORD
     JMP IipGroupSSE4:
.r64:IiAbortIfNot64
     IiEmitPrefix REX.W
     IiEncoding DATA=QWORD
     JMP IipGroupSSE4:
 ENDP IipPCMPESTRM::

↑ PCMPESTRI: Packed Compare Explicit Length Strings, Return Index
Modifier DATA=D | DATA=Q specifies if the implicit length registers are EAX,EDX | RAX,RDX.
Description: PCMPESTRI
Category: sse42,strtxt
Operands: rCX,Vdq,Wdq,...
Opcode: 0x660F3A61 /r
Flags: modified:O..SZAPC, defined:O..SZAPC, values:.....AP.
CPU: C2++
Documented: D⁴³
Tested by: t3820

IipPCMPESTRI:: PROC
    MOV CL,0x61
    JMP IipPCMPESTRM.op:
 ENDP IipPCMPESTRI::

↑ PCMPISTRM: Packed Compare Implicit Length Strings, Return Mask
Description: PCMPISTRM
Category: sse42,strtxt
Operands: XMM0,Vdq,Wdq,Ib
Opcode: 0x660F3A62 /r
Flags: modified:O..SZAPC, defined:O..SZAPC, values:.....AP.
CPU: C2++
Documented: D⁴³
Tested by: t3820

IipPCMPISTRM:: PROC
    MOV CL,0x62
.op:IiRequire SSE4.2
    JMP IipGroupSSE4:
 ENDP IipPCMPISTRM::

↑ PCMPISTRI: Packed Compare Implicit Length Strings, Return Index
Description: PCMPISTRI
Category: sse42,strtxt
Operands: rCX,Vdq,Wdq,Ib
Opcode: 0x660F3A63 /r
Flags: modified:O..SZAPC, defined:O..SZAPC, values:.....AP.
CPU: C2++
Documented: D⁴³
Tested by: t3820

IipPCMPISTRI:: PROC
    MOV CL,0x63
    JMP IipPCMPISTRM.op:
 ENDP IipPCMPISTRI::

↑ SHUFPS: Shuffle Packed Single-FP Values
Description: SHUFPS
Category: sse1,simdfp,shunpck
Operands: Vps,Wps,Ib
Opcode: 0x0FC6 /r
CPU: P3+
Tested by: t3755

IipSHUFPS:: PROC
    MOV CL,0xC6
.op:IiRequire 686,SSE2
    IiEncoding DATA=OWORD
    IiEmitOpcode 0x0F,ECX
    IiOpEn RM
    IiModRM /r
    IiEmitImm Operand3, BYTE, Max=7
    IiDispatchFormat xmm.xmm.imm, xmm.mem.imm
.xmm.xmm.imm:
.xmm.mem.imm:
    RET
 ENDP IipSHUFPS::

↑ PSHUFD: Shuffle Packed Doublewords
Description: PSHUFD
Category: sse2,simdint,shunpck
Operands: Vdq,Wdq,Ib
Opcode: 0x660F70 /r
CPU: P4+
Tested by: t3755

IipPSHUFD:: PROC
    IiEmitPrefix OTOGGLE
    MOV CL,0x70
    JMP IipSHUFPS.op:
 ENDP IipPSHUFD::

↑ SHUFPD: Shuffle Packed Double-FP Values
Description: SHUFPD
Category: sse2,pcksclr,shunpck
Operands: Vpd,Wpd,Ib
Opcode: 0x660FC6 /r
CPU: P4+
Tested by: t3755

IipSHUFPD:: PROC
    IiEmitPrefix OTOGGLE
    MOV CL,0xC6
    JMP IipSHUFPS.op:
 ENDP IipSHUFPD::

↑ PSHUFLW: Shuffle Packed Low Words
Description: PSHUFLW
Category: sse2,simdint,shunpck
Operands: Vdq,Wdq,Ib
Opcode: 0xF20F70 /r
CPU: P4+
Tested by: t3755

IipPSHUFLW:: PROC
    IiEmitPrefix REPNE
    MOV CL,0x70
    JMP IipSHUFPS.op:
 ENDP IipPSHUFLW::

↑ PSHUFHW: Shuffle Packed High Words
Description: PSHUFHW
Category: sse2,simdint,shunpck
Operands: Vdq,Wdq,Ib
Opcode: 0xF30F70 /r
CPU: P4+
Tested by: t3755

IipPSHUFHW:: PROC
    IiEmitPrefix REPE
    MOV CL,0x70
    JMP IipSHUFPS.op:
 ENDP IipPSHUFHW::

↑ MOVDQA: Move Aligned Double Quadword
Description: MOVDQA
Category: sse2,simdint,datamov
Operands: Vdq,Wdq | Wdq,Vdq
Opcode: 0x660F6F /r | 0x660F7F /r
CPU: P4+
Tested by: t3785

IipMOVDQA:: PROC
    IiEmitPrefix OTOGGLE
.pf:IiRequire 686,SSE2
    IiAllowModifier CODE
    IiEmitOpcode 0x0F
    IiModRM /r
    IiDispatchFormat xmm.mem, mem.xmm, xmm.xmm
.mem.xmm:
    IiEmitOpcode 0x7F
    IiEncoding CODE=LONG,DATA=OWORD
    IiOpEn MR
    RET
.xmm.xmm:
    IiDispatchCode LONG=.mem.xmm:
.xmm.mem:
    IiEmitOpcode 0x6F
    IiEncoding CODE=SHORT,DATA=OWORD
    IiOpEn RM
    RET
 ENDP IipMOVDQA::

↑ MOVDQU: Move Unaligned Double Quadword
Description: MOVDQU
Category: sse2,simdint,datamov
Operands: Vdq,Wdq | Wdq,Vdq
Opcode: 0xF30F6F /r | 0xF30F7F /r
CPU: P4+
Tested by: t3785

IipMOVDQU:: PROC
    IiEmitPrefix REPE
    JMP IipMOVDQA.pf:
 ENDP IipMOVDQU::

↑ MASKMOVDQU: Store Selected Bytes of Double Quadword
Description: MASKMOVDQU
Category: sse2,cachect
Operands: mmx,mmx or [ES:rDI],xmm,xmm
Opcode: 0x660FF7 /r
CPU: P4+
Tested by: t3780

IipMASKMOVDQU:: PROC
    IiRequire 686,SSE2
    IiEncoding DATA=OWORD
    IiEmitPrefix OTOGGLE
    IiEmitOpcode 0x0F,0xF7
    IiDispatchFormat xmm.xmm, mem.xmm.xmm
.mem.xmm.xmm:
    IiStringDestination Operand1, AllowSeg=YES
    IiSwap Operand1,Operand2 ; Get rid of Operand1.
    IiSwap Operand2,Operand3
.xmm.xmm:
    IiOpEn RM
    IiModRM /r
    RET
 ENDP IipMASKMOVDQU::

↑ LDDQU: Load Unaligned Integer 128 Bits
Description: LDDQU
Category: sse3,cachect
Operands: Vdq,Mdq
Opcode: 0xF20FF0 /r
CPU: P4++
Tested by: t3790

IipLDDQU:: PROC
    IiRequire 686,SSE3
    IiEncoding DATA=OWORD
    IiEmitPrefix REPNE
    IiEmitOpcode 0x0F,0xF0
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat xmm.mem
.xmm.mem:
    RET
 ENDP IipLDDQU::

↑ IipGroupCLMUL: IipGroupCLMUL is a common handler for carry-less instructions in format xmm,xmm/m128,imm8 encoded with prefix 0x66 and three-byte opcode 0x0F, 0x3A, 0x44.
Input: CL is immediate value which selects quadwords to operate on.
EDX has operand types as set by IiAssemble with eliminated 3rd immediate operand.
EDI is pointer to II structure with parsed operands.
Tested by: t3875

IipGroupCLMUL:: PROC
    IiRequire 686,SSE4
    IiEncoding DATA=QWORD
    IiEncoding DATA=OWORD,IMM=BYTE
    MOV [EDI+II.ImmLow],CL
    IiEmitPrefix OTOGGLE
    IiEmitOpcode 0x0F,0x3A,0x44
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat xmm.xmm, xmm.mem
.xmm.xmm:
.xmm.mem:
    RET
 ENDP IipGroupCLMUL::

↑ PCLMULQDQ: Carry-Less Multiplication Qword
Description: PCLMULQDQ
Category: SSE, CLMUL
Operands: xmm, xmm/m128, imm8
Opcode: 0x660F3A44 /r ib
Tested by: t3875

IipPCLMULQDQ:: PROC
     IiDispatchFormat xmm.xmm.imm, xmm.mem.imm
.xmm.xmm.imm:
.xmm.mem.imm:
     SHR EDX,8 ; Eliminate imm operand.
     MOV ECX,[EDI+II.Operand3+EXP.Low]
     JMP IipGroupCLMUL:
 ENDP IipPCLMULQDQ::

↑ PCLMULLQLQDQ: Carry-Less Multiplication Qword imm=0x00
Category: SSE, CLMUL
Operands: xxm, xxm/m128
Opcode: 0x660F3A44/r00
Tested by: t3875

IipPCLMULLQLQDQ:: PROC
    MOV CL,0x00
    JMP IipGroupCLMUL:
 ENDP IipPCLMULLQLQDQ::

↑ PCLMULHQLQDQ: Carry-Less Multiplication Qword imm=0x01
Category: SSE, CLMUL
Operands: xxm, xxm/m128
Opcode: 0x660F3A44/r01
Tested by: t3875

IipPCLMULHQLQDQ:: PROC
    MOV CL,0x01
    JMP IipGroupCLMUL:
 ENDP IipPCLMULHQLQDQ::

↑ PCLMULLQHQDQ: Carry-Less Multiplication Qword imm=0x10
Category: SSE, CLMUL
Operands: xxm, xxm/m128
Opcode: 0x660F3A44/r10
Tested by: t3875

IipPCLMULLQHQDQ:: PROC
    MOV CL,0x10
    JMP IipGroupCLMUL:
 ENDP IipPCLMULLQHQDQ::

↑ PCLMULHQHQDQ: Carry-Less Multiplication Qword imm=0x11
Category: SSE, CLMUL
Operands: xxm, xxm/m128
Opcode: 0x660F3A44/r11
Tested by: t3875

IipPCLMULHQHQDQ:: PROC
    MOV CL,0x11
    JMP IipGroupCLMUL:
 ENDP IipPCLMULHQHQDQ::

↑ IipGroupBLEND: IipGroupBLEND is a common handler for SSE4.1 blending instructions in format xmm,xmm/m128,XMM0 encoded with prefix 0x66 and three-byte opcode 0x0F, 0x38, CL.
The third operand (XMM0) may be omitted.
Input: CL is tertiary opcode.
EDX has operand types as set by IiAssemble with eliminated 3rd immediate operand.
EDI is pointer to II structure with parsed operands.
Tested by: t3825

IipGroupBLEND:: PROC
    IiRequire 686,SSE4.1
    IiEncoding DATA=QWORD
    IiEmitPrefix OTOGGLE
    IiEmitOpcode 0x0F,0x38,ECX
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat xmm.xmm, xmm.mem, xmm.xmm.xmm, xmm.mem.xmm
.xmm.xmm.xmm:
.xmm.mem.xmm:
     IiAbortIfNot Operand3,XMM0
.xmm.xmm:
.xmm.mem:
    RET
 ENDP IipGroupBLEND::

↑ PBLENDVB: Variable Blend Packed Bytes
Description: PBLENDVB
Category: sse41,simdint,datamov
Operands: Vdq,Wdq,XMM0
Opcode: 0x660F3810 /r
CPU: C2++
Documented: D⁴³
Tested by: t3825

IipPBLENDVB:: PROC
    MOV CL,0x10
    JMP IipGroupBLEND
 ENDP IipPBLENDVB::

↑ BLENDVPS: Variable Blend Packed Single-FP Values
Description: BLENDVPS
Category: sse41,simdint,datamov
Operands: Vps,Wps,XMM0
Opcode: 0x660F3814 /r
CPU: C2++
Documented: D⁴³
Tested by: t3825

IipBLENDVPS:: PROC
    MOV CL,0x14
    JMP IipGroupBLEND
 ENDP IipBLENDVPS::

↑ BLENDVPD: Variable Blend Packed Double-FP Values
Description: BLENDVPD
Category: sse41,simdint,datamov
Operands: Vpd,Wpd,XMM0
Opcode: 0x660F3815 /r
CPU: C2++
Documented: D⁴³
Tested by: t3825

IipBLENDVPD:: PROC
    MOV CL,0x15
    JMP IipGroupBLEND
 ENDP IipBLENDVPD::

↑ CMPSS: Compare Scalar Single-FP Values
Description: CMPSS
Category: sse1,simdfp,compar
Operands: Vss,Wss,Ib
Opcode: 0xF30FC2 /r
CPU: P3+

IipCMPSS:: PROC
    IiRequire SSE1
    IiEncoding DATA=DWORD
    IiEmitPrefix REPE
    IiEmitOpcode 0x0F,0xC2
    IiOpEn RM
    IiModRM /r
    IiEmitImm Operand3, BYTE, Max=7
    IiDispatchFormat xmm.xmm.imm, xmm.mem.imm
.xmm.xmm.imm:
.xmm.mem.imm
    RET
.cc:IiImmCreate CL,OpPosition=Operand3 ; Entry for CL=cc from mnemonic.
    JMP IipCMPSS:    
 ENDP IipCMPSS::

↑ CMPEQSS: Compare Scalar Single-FP values Equal
Category: sse1,simdfp, compar
Operands: xmm, xmm/mem128
Opcode: 0xF30FC2 /r 0x00
CPU: P3+
Tested by: t3882

IipCMPEQSS:: PROC
    MOV CL,0x00
    JMP IipCMPSS.cc:
 ENDP IipCMPEQSS::

↑ CMPLTSS: Compare Scalar Single-FP values Less Than
Category: sse1,simdfp, compar
Operands: xmm, xmm/mem128
Opcode: 0xF30FC2 /r 0x01
CPU: P3+
Tested by: t3882

IipCMPLTSS:: PROC
    MOV CL,0x01
    JMP IipCMPSS.cc:
 ENDP IipCMPLTSS::

↑ CMPLESS: Compare Scalar Single-FP values Less than or Equal
Category: sse1,simdfp, compar
Operands: xmm, xmm/mem128
Opcode: 0xF30FC2 /r 0x02
CPU: P3+
Tested by: t3882

IipCMPLESS:: PROC
    MOV CL,0x02
    JMP IipCMPSS.cc:
 ENDP IipCMPLESS::

↑ CMPUNORDSS: Compare Scalar Single-FP values Unordered
Category: sse1,simdfp, compar
Operands: xmm, xmm/mem128
Opcode: 0xF30FC2 /r 0x03
CPU: P3+
Tested by: t3882

IipCMPUNORDSS:: PROC
    MOV CL,0x03
    JMP IipCMPSS.cc:
 ENDP IipCMPUNORDSS::

↑ CMPNEQSS: Compare Scalar Single-FP values Not Equal
Category: sse1,simdfp, compar
Operands: xmm, xmm/mem128
Opcode: 0xF30FC2 /r 0x04
CPU: P3+
Tested by: t3882

IipCMPNEQSS:: PROC
    MOV CL,0x04
    JMP IipCMPSS.cc:
 ENDP IipCMPNEQSS::

↑ CMPNLTSS: Compare Scalar Single-FP values Not Less Than
Category: sse1,simdfp, compar
Operands: xmm, xmm/mem128
Opcode: 0xF30FC2 /r 0x05
CPU: P3+
Tested by: t3882

IipCMPNLTSS:: PROC
    MOV CL,0x05
    JMP IipCMPSS.cc:
 ENDP IipCMPNLTSS::

↑ CMPNLESS: Compare Scalar Single-FP values Not Less than or Equal
Category: sse1,simdfp, compar
Operands: xmm, xmm/mem128
Opcode: 0xF30FC2 /r 0x06
CPU: P3+
Tested by: t3882

IipCMPNLESS:: PROC
    MOV CL,0x06
    JMP IipCMPSS.cc:
 ENDP IipCMPNLESS::

↑ CMPORDSS: Compare Scalar Single-FP values Ordered
Category: sse1,simdfp, compar
Operands: xmm, xmm/mem128
Opcode: 0xF30FC2 /r 0x07
CPU: P3+
Tested by: t3882

IipCMPORDSS:: PROC
    MOV CL,0x07
    JMP IipCMPSS.cc:
 ENDP IipCMPORDSS::

↑ CMPPS: Compare Packed Single-FP Values
Description: CMPPS
Category: sse1,simdfp,compar
Operands: Vps,Wps,Ib
Opcode: 0x0FC2 /r
CPU: P3+
Tested by: t3884

IipCMPPS:: PROC
    IiRequire SSE1
    IiEncoding DATA=DWORD
    IiEmitOpcode 0x0F,0xC2
    IiOpEn RM
    IiModRM /r
    IiEmitImm Operand3, BYTE, Max=7
    IiDispatchFormat xmm.xmm.imm, xmm.mem.imm
.xmm.xmm.imm:
.xmm.mem.imm
    RET
.cc:IiImmCreate CL,OpPosition=Operand3 ; Entry for CL=cc from mnemonic.
    JMP IipCMPPS:    
 ENDP IipCMPPS::

↑ CMPEQPS: Compare Packed Single-FP values Equal
Category: sse1,simdfp, compar
Operands: xmm, xmm/mem128
Opcode: 0x0FC2 /r 0x00
CPU: P3+
Tested by: t3884

IipCMPEQPS:: PROC
    MOV CL,0x00
    JMP IipCMPPS.cc:
 ENDP IipCMPEQPS::

↑ CMPLTPS: Compare Packed Single-FP values Less Than
Category: sse1,simdfp, compar
Operands: xmm, xmm/mem128
Opcode: 0x0FC2 /r 0x01
CPU: P3+
Tested by: t3884

IipCMPLTPS:: PROC
    MOV CL,0x01
    JMP IipCMPPS.cc:
 ENDP IipCMPLTPS::

↑ CMPLEPS: Compare Packed Single-FP values Less than or Equal
Category: sse1,simdfp, compar
Operands: xmm, xmm/mem128
Opcode: 0x0FC2 /r 0x02
CPU: P3+
Tested by: t3884

IipCMPLEPS:: PROC
    MOV CL,0x02
    JMP IipCMPPS.cc:
 ENDP IipCMPLEPS::

↑ CMPUNORDPS: Compare Packed Single-FP values Unordered
Category: sse1,simdfp, compar
Operands: xmm, xmm/mem128
Opcode: 0x0FC2 /r 0x03
CPU: P3+
Tested by: t3884

IipCMPUNORDPS:: PROC
    MOV CL,0x03
    JMP IipCMPPS.cc:
 ENDP IipCMPUNORDPS::

↑ CMPNEQPS: Compare Packed Single-FP values Not Equal
Category: sse1,simdfp, compar
Operands: xmm, xmm/mem128
Opcode: 0x0FC2 /r 0x04
CPU: P3+
Tested by: t3884

IipCMPNEQPS:: PROC
    MOV CL,0x04
    JMP IipCMPPS.cc:
 ENDP IipCMPNEQPS::

↑ CMPNLTPS: Compare Packed Single-FP values Not Less Than
Category: sse1,simdfp, compar
Operands: xmm, xmm/mem128
Opcode: 0x0FC2 /r 0x05
CPU: P3+
Tested by: t3884

IipCMPNLTPS:: PROC
    MOV CL,0x05
    JMP IipCMPPS.cc:
 ENDP IipCMPNLTPS::

↑ CMPNLEPS: Compare Packed Single-FP values Not Less than or Equal
Category: sse1,simdfp, compar
Operands: xmm, xmm/mem128
Opcode: 0x0FC2 /r 0x06
CPU: P3+
Tested by: t3884

IipCMPNLEPS:: PROC
    MOV CL,0x06
    JMP IipCMPPS.cc:
 ENDP IipCMPNLEPS::

↑ CMPORDPS: Compare Packed Single-FP values Ordered
Category: sse1,simdfp, compar
Operands: xmm, xmm/mem128
Opcode: 0x0FC2 /r 0x07
CPU: P3+
Tested by: t3884

IipCMPORDPS:: PROC
    MOV CL,0x07
    JMP IipCMPPS.cc:
 ENDP IipCMPORDPS::

↑ CMPSD: Compare Packed Double-FP Values / overloaded as Compare string operands, DATA=D
Description: CMPSD
Category: sse2,pcksclr,compar
Operands: Vpd,Wpd,Ib
Opcode: 0x660FC2 /r
CPU: P4+
Tested by: t3886

IipCMPSD:: PROC
    IiRequire SSE2
    IiEncoding DATA=QWORD
    IiEmitPrefix REPNE
    IiEmitOpcode 0x0F,0xC2
    IiOpEn RM
    IiModRM /r
    IiEmitImm Operand3, BYTE, Max=7
    IiDispatchFormat xmm.xmm.imm, xmm.mem.imm
.xmm.xmm.imm:
.xmm.mem.imm
    RET
.cc:IiImmCreate CL,OpPosition=Operand3 ; Entry for CL=cc from mnemonic.
    JMP IipCMPSD:    
 ENDP IipCMPSD::

↑ CMPEQSD: Compare Scalar Double-FP values Equal
Category: sse2,pcksclr,compar
Operands: xmm, xmm/mem128
Opcode: 0xF20FC2 /r 0x00
CPU: P4+
Tested by: t3886

IipCMPEQSD:: PROC
    MOV CL,0x00
    JMP IipCMPSD.cc:
 ENDP IipCMPEQSD::

↑ CMPLTSD: Compare Scalar Double-FP values Less Than
Category: sse2,pcksclr,compar
Operands: xmm, xmm/mem128
Opcode: 0xF20FC2 /r 0x01
CPU: P4+
Tested by: t3886

IipCMPLTSD:: PROC
    MOV CL,0x01
    JMP IipCMPSD.cc:
 ENDP IipCMPLTSD::

↑ CMPLESD: Compare Scalar Double-FP values Less than or Equal
Category: sse2,pcksclr,compar
Operands: xmm, xmm/mem128
Opcode: 0xF20FC2 /r 0x02
CPU: P4+
Tested by: t3886

IipCMPLESD:: PROC
    MOV CL,0x02
    JMP IipCMPSD.cc:
 ENDP IipCMPLESD::

↑ CMPUNORDSD: Compare Scalar Double-FP values Unordered
Category: sse2,pcksclr,compar
Operands: xmm, xmm/mem128
Opcode: 0xF20FC2 /r 0x03
CPU: P4+
Tested by: t3886

IipCMPUNORDSD:: PROC
    MOV CL,0x03
    JMP IipCMPSD.cc:
 ENDP IipCMPUNORDSD::

↑ CMPNEQSD: Compare Scalar Double-FP values Not Equal
Category: sse2,pcksclr,compar
Operands: xmm, xmm/mem128
Opcode: 0xF20FC2 /r 0x04
CPU: P4+
Tested by: t3886

IipCMPNEQSD:: PROC
    MOV CL,0x04
    JMP IipCMPSD.cc:
 ENDP IipCMPNEQSD::

↑ CMPNLTSD: Compare Scalar Double-FP values Not Less Than
Category: sse2,pcksclr,compar
Operands: xmm, xmm/mem128
Opcode: 0xF20FC2 /r 0x05
CPU: P4+
Tested by: t3886

IipCMPNLTSD:: PROC
    MOV CL,0x05
    JMP IipCMPSD.cc:
 ENDP IipCMPNLTSD::

↑ CMPNLESD: Compare Scalar Double-FP values Not Less than or Equal
Category: sse2,pcksclr,compar
Operands: xmm, xmm/mem128
Opcode: 0xF20FC2 /r 0x06
CPU: P4+
Tested by: t3886

IipCMPNLESD:: PROC
    MOV CL,0x06
    JMP IipCMPSD.cc:
 ENDP IipCMPNLESD::

↑ CMPORDSD: Compare Scalar Double-FP values Ordered
Category: sse2,pcksclr,compar
Operands: xmm, xmm/mem128
Opcode: 0xF20FC2 /r 0x07
CPU: P4+
Tested by: t3886

IipCMPORDSD:: PROC
    MOV CL,0x07
    JMP IipCMPSD.cc:
 ENDP IipCMPORDSD::

↑ CMPPD: Compare Packed Double-FP Values
Description: CMPPD
Category: sse2,pcksclr,compar
Operands: Vpd,Wpd,Ib
Opcode: 0x660FC2 /r
CPU: P4+
Tested by: t3888

IipCMPPD:: PROC
    IiRequire SSE2
    IiEncoding DATA=QWORD
    IiEmitPrefix OTOGGLE
    IiEmitOpcode 0x0F,0xC2
    IiOpEn RM
    IiModRM /r
    IiEmitImm Operand3, BYTE, Max=7
    IiDispatchFormat xmm.xmm.imm, xmm.mem.imm
.xmm.xmm.imm:
.xmm.mem.imm
    RET
.cc:IiImmCreate CL,OpPosition=Operand3 ; Entry for CL=cc from mnemonic.
    JMP IipCMPPD:    
 ENDP IipCMPPD::

↑ CMPEQPD: Compare Packed Double-FP values Equal
Category: sse2,pcksclr,compar
Operands: xmm, xmm/mem128
Opcode: 0x660FC2 /r 0x00
CPU: P4+
Tested by: t3888

IipCMPEQPD:: PROC
    MOV CL,0x00
    JMP IipCMPPD.cc:
 ENDP IipCMPEQPD::

↑ CMPLTPD: Compare Packed Double-FP values Less Than
Category: sse2,pcksclr,compar
Operands: xmm, xmm/mem128
Opcode: 0x660FC2 /r 0x01
CPU: P4+
Tested by: t3888

IipCMPLTPD:: PROC
    MOV CL,0x01
    JMP IipCMPPD.cc:
 ENDP IipCMPLTPD::

↑ CMPLEPD: Compare Packed Double-FP values Less than or Equal
Category: sse2,pcksclr,compar
Operands: xmm, xmm/mem128
Opcode: 0x660FC2 /r 0x02
CPU: P4+
Tested by: t3888

IipCMPLEPD:: PROC
    MOV CL,0x02
    JMP IipCMPPD.cc:
 ENDP IipCMPLEPD::

↑ CMPUNORDPD: Compare Packed Double-FP values Unordered
Category: sse2,pcksclr,compar
Operands: xmm, xmm/mem128
Opcode: 0x660FC2 /r 0x03
CPU: P4+
Tested by: t3888

IipCMPUNORDPD:: PROC
    MOV CL,0x03
    JMP IipCMPPD.cc:
 ENDP IipCMPUNORDPD::

↑ CMPNEQPD: Compare Packed Double-FP values Not Equal
Category: sse2,pcksclr,compar
Operands: xmm, xmm/mem128
Opcode: 0x660FC2 /r 0x04
CPU: P4+
Tested by: t3888

IipCMPNEQPD:: PROC
    MOV CL,0x04
    JMP IipCMPPD.cc:
 ENDP IipCMPNEQPD::

↑ CMPNLTPD: Compare Packed Double-FP values Not Less Than
Category: sse2,pcksclr,compar
Operands: xmm, xmm/mem128
Opcode: 0x660FC2 /r 0x05
CPU: P4+
Tested by: t3888

IipCMPNLTPD:: PROC
    MOV CL,0x05
    JMP IipCMPPD.cc:
 ENDP IipCMPNLTPD::

↑ CMPNLEPD: Compare Packed Double-FP values Not Less than or Equal
Category: sse2,pcksclr,compar
Operands: xmm, xmm/mem128
Opcode: 0x660FC2 /r 0x06
CPU: P4+
Tested by: t3888

IipCMPNLEPD:: PROC
    MOV CL,0x06
    JMP IipCMPPD.cc:
 ENDP IipCMPNLEPD::

↑ CMPORDPD: Compare Packed Double-FP values Ordered
Category: sse2,pcksclr,compar
Operands: xmm, xmm/mem128
Opcode: 0x660FC2 /r 0x07
CPU: P4+
Tested by: t3888

IipCMPORDPD:: PROC
    MOV CL,0x07
    JMP IipCMPPD.cc:
 ENDP IipCMPORDPD::

↑ MOVNTSS: Move Non-Temporal Scalar Single-Precision Floating-Point
Category: SSE4 AMD
Operands: mem32, xmm
Opcode: F3042B /r
Tested by: t3685

IipMOVNTSS:: PROC
    IiRequire 686,SSE4,AMD
    IiEncoding DATA=DWORD
    IiEmitPrefix REPE
    IiEmitOpcode 0x0F,0x2B
    IiOpEn MR
    IiModRM /r
    IiDispatchFormat mem.xmm
.mem.xmm:
    RET
 ENDP IipMOVNTSS::

↑ MOVNTSD: Move Non-Temporal Scalar Double-Precision Floating-Point
Category: SSE4 AMD
Operands: mem64,xmm
Opcode: 0xF20F2B /r
Tested by: t3685

IipMOVNTSD:: PROC
    IiRequire 686,SSE4,AMD
    IiEncoding DATA=QWORD
    IiEmitPrefix REPNE
    IiEmitOpcode 0x0F,0x2B
    IiOpEn MR
    IiModRM /r
    IiDispatchFormat mem.xmm
.mem.xmm:
    RET
 ENDP IipMOVNTSD::

↑ EXTRQ: Extract Field From Register
Category: SSE4 AMD
Operands: xmm,xmm | xmm,imm8,imm8
Opcode: 660F79 /r | 660F78 /0 ib ib
Tested by: t3775

IipEXTRQ:: PROC
    IiRequire 686,SSE4,AMD
    IiEmitPrefix OTOGGLE
    IiEmitOpcode 0x0F
    IiDispatchFormat xmm.xmm, xmm.imm.imm
.xmm.xmm:
    IiEmitOpcode 0x79
    IiOpEn RM
    IiModRM /r
    RET
.xmm.imm.imm:
    IiEmitOpcode 0x78
    IiOpEn M
    IiModRM /0
    IiEmitImm Operand2, BYTE
    IiEmitImm2 Operand3
    RET
 ENDP IipEXTRQ::

↑ INSERTQ: Insert Field
Category: SSE4 AMD
Operands: xmm,xmm,imm8,imm8 | xmm,xmm
Opcode: 0xF20F78 /r ib ib | 0xF20F79 /r
Tested by: t3775

IipINSERTQ:: PROC
    IiRequire 686,SSE4,AMD
    IiEmitPrefix REPNE
    IiEmitOpcode 0x0F
    IiModRM /r
    IiDispatchFormat xmm.xmm, xmm.xmm.imm.imm
.xmm.xmm:
    IiEmitOpcode 0x79
    IiOpEn RM
    RET
.xmm.xmm.imm.imm:
    IiEmitOpcode 0x78
    IiOpEn MR ; AMD does not specify operand encoding, NASM uses MR here.
    IiEmitImm Operand3, BYTE
    IiEmitImm2 Operand4
    RET
 ENDP IipINSERTQ::

  ENDPROGRAM iip

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